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Core_PWM,verilog语言编写

    DFN1C1 \counter[19]  (.D(\counter_5[19]_net_1 ), .CLK(GLA), .CLR(
        rst_c), .Q(\counter[19]_net_1 ));
    OR2A un1_counter_0_I_78 (.A(\clock_divide_r[26]_net_1 ), .B(
        \counter[26]_net_1 ), .Y(\ACT_LT3_E_0[4] ));
    DFN1E0C1 \duty_cycle_r[17]  (.D(data[1]), .CLK(GLA), .CLR(rst_c), 
        .E(duty_cycle_r_56_e_net_1), .Q(\duty_cycle_r[17]_net_1 ));
    AND2 un8_counter_I_94 (.A(\DWACT_FINC_E[7] ), .B(\DWACT_FINC_E[9] )
        , .Y(\DWACT_FINC_E[10] ));
    AND3 un8_counter_I_152 (.A(\DWACT_FINC_E[34] ), .B(
        \DWACT_FINC_E[2] ), .C(\DWACT_FINC_E[5] ), .Y(
        \DWACT_FINC_E[29] ));
    XNOR2 un1_duty_cycle_r_0_I_9 (.A(\duty_cycle_r[24]_net_1 ), .B(
        \counter[24]_net_1 ), .Y(\DWACT_BL_EQUAL_0_E_0[5] ));
    DFN1E0C1 \clock_divide_r[24]  (.D(data[0]), .CLK(GLA), .CLR(rst_c), 
        .E(N_283_i), .Q(\clock_divide_r[24]_net_1 ));
    OR2A un1_duty_cycle_r_0_I_221 (.A(\counter[1]_net_1 ), .B(
        \duty_cycle_r[1]_net_1 ), .Y(N_16));
    NOR2 duty_cycle_r_48_e_0 (.A(un1_duty_cycle_r34_net_1), .B(addr[1])
        , .Y(duty_cycle_r_48_e_0_net_1));
    NOR2A un1_counter_0_I_51 (.A(\clock_divide_r[27]_net_1 ), .B(
        \counter[27]_net_1 ), .Y(N_134_0));
    DFN1E0C1 \duty_cycle_r[6]  (.D(data[6]), .CLK(GLA), .CLR(rst_c), 
        .E(duty_cycle_r_40_e_net_1), .Q(\duty_cycle_r[6]_net_1 ));
    XNOR2 un1_duty_cycle_r_0_I_34 (.A(\duty_cycle_r[31]_net_1 ), .B(
        \counter[31]_net_1 ), .Y(\DWACT_BL_EQUAL_0_E_1[4] ));
    OA1A un1_duty_cycle_r_0_I_230 (.A(N_20), .B(N_22), .C(N_21), .Y(
        N_25));
    AND3 un8_counter_I_121 (.A(\DWACT_FINC_E[28] ), .B(
        \DWACT_FINC_E[13] ), .C(\counter[18]_net_1 ), .Y(N_76));
    OR2A un1_duty_cycle_r_0_I_204 (.A(\counter[6]_net_1 ), .B(
        \duty_cycle_r[6]_net_1 ), .Y(N_32));
    NOR2B \counter_5[30]  (.A(I_217), .B(I_248_0), .Y(
        \counter_5[30]_net_1 ));
    NOR2B \counter_5[24]  (.A(I_166), .B(I_248_0), .Y(
        \counter_5[24]_net_1 ));
    DFN1C1 \counter[28]  (.D(\counter_5[28]_net_1 ), .CLK(GLA), .CLR(
        rst_c), .Q(\counter[28]_net_1 ));
    AO1 un1_duty_cycle_r_0_I_238 (.A(
        \DWACT_CMPLE_PO2_DWACT_COMP0_E_2[1] ), .B(
        \DWACT_CMPLE_PO2_DWACT_COMP0_E_1[2] ), .C(
        \DWACT_CMPLE_PO2_DWACT_COMP0_E_1[0] ), .Y(
        \DWACT_CMPLE_PO2_DWACT_COMP0_E_0[2] ));
    XNOR2 un1_counter_0_I_136 (.A(\counter[16]_net_1 ), .B(
        \clock_divide_r[16]_net_1 ), .Y(\DWACT_BL_EQUAL_0_E_6[1] ));
    OA1A un1_counter_0_I_171 (.A(\counter[13]_net_1 ), .B(
        \clock_divide_r[13]_net_1 ), .C(N_61_1), .Y(N_65_0));
    AOI1A un1_counter_0_I_159 (.A(\ACT_LT4_E_0[3] ), .B(
        \ACT_LT4_E_0[6] ), .C(\ACT_LT4_E_0[10] ), .Y(
        \DWACT_CMPLE_PO0_DWACT_COMP0_E_1[0] ));
    XOR2 un8_counter_I_84 (.A(N_103), .B(\counter[14]_net_1 ), .Y(I_84)
        );
    XOR2 un8_counter_I_143 (.A(N_61), .B(\counter[22]_net_1 ), .Y(
        I_143));
    XNOR2 un1_duty_cycle_r_0_I_4 (.A(\duty_cycle_r[22]_net_1 ), .B(
        \counter[22]_net_1 ), .Y(\DWACT_BL_EQUAL_0_E_3[3] ));
    OR2A un1_counter_0_I_153 (.A(\clock_divide_r[17]_net_1 ), .B(
        \counter[17]_net_1 ), .Y(\ACT_LT4_E_0[4] ));
    DFN1E0C1 \duty_cycle_r[23]  (.D(data[7]), .CLK(GLA), .CLR(rst_c), 
        .E(duty_cycle_r_56_e_net_1), .Q(\duty_cycle_r[23]_net_1 ));
    DFN1E0C1 \clock_divide_r[7]  (.D(data[7]), .CLK(GLA), .CLR(rst_c), 
        .E(clock_divide_r_8_e_net_1), .Q(\clock_divide_r[7]_net_1 ));
    OA1A un1_counter_0_I_175 (.A(N_64_0), .B(N_66_1), .C(N_65_0), .Y(
        N_69_0));
    AO1 un1_counter_0_I_248 (.A(\DWACT_COMP0_E[1] ), .B(I_243), .C(
        \DWACT_COMP0_E[0] ), .Y(I_248));
    XNOR2 un1_counter_0_I_190 (.A(\counter[7]_net_1 ), .B(
        \clock_divide_r[7]_net_1 ), .Y(\DWACT_BL_EQUAL_0_E_5[2] ));
    AND3 un1_counter_0_I_14 (.A(\DWACT_BL_EQUAL_0_E_10[0] ), .B(
        \DWACT_BL_EQUAL_0_E_10[1] ), .C(\DWACT_BL_EQUAL_0_E_10[2] ), 
        .Y(\DWACT_BL_EQUAL_0_DWACT_ANDTREE_E_8[0] ));
    AND3 un8_counter_I_132 (.A(\counter[18]_net_1 ), .B(
        \counter[19]_net_1 ), .C(\counter[20]_net_1 ), .Y(
        \DWACT_FINC_E[15] ));
    DFN1E0C1 \duty_cycle_r[18]  (.D(data[2]), .CLK(GLA), .CLR(rst_c), 
        .E(duty_cycle_r_56_e_net_1), .Q(\duty_cycle_r[18]_net_1 ));
    AND3 un8_counter_I_48 (.A(\DWACT_FINC_E[0] ), .B(\DWACT_FINC_E[2] )
        , .C(\DWACT_FINC_E[3] ), .Y(\DWACT_FINC_E[4] ));
    OA1A un1_duty_cycle_r_0_I_209 (.A(\duty_cycle_r[8]_net_1 ), .B(
        \counter[8]_net_1 ), .C(N_33), .Y(N_37_0));
    XNOR2 un1_duty_cycle_r_0_I_119 (.A(\duty_cycle_r[10]_net_1 ), .B(
        \counter[10]_net_1 ), .Y(\DWACT_BL_EQUAL_0_E_1[0] ));
    DFN1E0C1 \clock_divide_r[9]  (.D(data[1]), .CLK(GLA), .CLR(rst_c), 
        .E(N_251_i), .Q(\clock_divide_r[9]_net_1 ));
    OA1A un1_duty_cycle_r_0_I_171 (.A(\duty_cycle_r[13]_net_1 ), .B(
        \counter[13]_net_1 ), .C(N_61_0), .Y(N_65));
    XNOR2 un1_duty_cycle_r_0_I_122 (.A(\duty_cycle_r[11]_net_1 ), .B(
        \counter[11]_net_1 ), .Y(\DWACT_BL_EQUAL_0_E_1[1] ));
    OR3A duty_cycle_r_56_e (.A(addr[1]), .B(addr[0]), .C(
        un1_duty_cycle_r34_net_1), .Y(duty_cycle_r_56_e_net_1));
    NOR2B \counter_5[19]  (.A(I_122), .B(I_248_1), .Y(
        \counter_5[19]_net_1 ));
    DFN1C1 \counter[29]  (.D(\counter_5[29]_net_1 ), .CLK(GLA), .CLR(
        rst_c), .Q(\counter[29]_net_1 ));
    XOR2 un8_counter_I_13 (.A(N_154), .B(\counter[3]_net_1 ), .Y(
        I_13_0));
    AO1C un1_duty_cycle_r_0_I_208 (.A(\counter[6]_net_1 ), .B(
        \duty_cycle_r[6]_net_1 ), .C(N_34), .Y(N_36_0));
    OR2A un1_duty_cycle_r_0_I_49 (.A(\counter[28]_net_1 ), .B(
        \duty_cycle_r[28]_net_1 ), .Y(N_132));
    XNOR2 un1_duty_cycle_r_0_I_2 (.A(\duty_cycle_r[27]_net_1 ), .B(
        \counter[27]_net_1 ), .Y(\DWACT_BL_EQUAL_0_E_0[8] ));
    NOR2B \counter_5[20]  (.A(I_129), .B(I_248_1), .Y(
        \counter_5[20]_net_1 ));
    NOR2B \counter_5[11]  (.A(I_66), .B(I_248_1), .Y(
        \counter_5[11]_net_1 ));
    DFN1C1 \counter[11]  (.D(\counter_5[11]_net_1 ), .CLK(GLA), .CLR(
        rst_c), .Q(\counter[11]_net_1 ));
    NOR2A un1_counter_0_I_206 (.A(\clock_divide_r[5]_net_1 ), .B(
        \counter[5]_net_1 ), .Y(N_34_0));
    AO1 un1_counter_0_I_109 (.A(\DWACT_CMPLE_PO0_DWACT_COMP0_E_2[1] ), 
        .B(\DWACT_CMPLE_PO0_DWACT_COMP0_E_2[2] ), .C(
        \DWACT_CMPLE_PO0_DWACT_COMP0_E_2[0] ), .Y(\DWACT_COMP0_E[0] ));
    NOR2A un1_counter_0_I_223 (.A(\clock_divide_r[0]_net_1 ), .B(
        \counter[0]_net_1 ), .Y(N_18_0));
    AND3 un8_counter_I_55 (.A(\DWACT_FINC_E[4] ), .B(
        \counter[8]_net_1 ), .C(\counter[9]_net_1 ), .Y(N_123));
    OR2 clock_divide_r_8_e (.A(N_261), .B(un1_duty_cycle_r34_1_net_1), 
        .Y(clock_divide_r_8_e_net_1));
    AND3 un8_counter_I_118 (.A(\DWACT_FINC_E[7] ), .B(
        \DWACT_FINC_E[9] ), .C(\DWACT_FINC_E[12] ), .Y(
        \DWACT_FINC_E[13] ));
    OR2A un1_duty_cycle_r_0_I_157 (.A(\duty_cycle_r[18]_net_1 ), .B(
        \counter[18]_net_1 ), .Y(\ACT_LT4_E[8] ));
    XNOR2 un1_counter_0_I_114 (.A(\counter[18]_net_1 ), .B(
        \clock_divide_r[18]_net_1 ), .Y(\DWACT_BL_EQUAL_0_E_1[8] ));
    DFN1E0C1 \duty_cycle_r[26]  (.D(data[2]), .CLK(GLA), .CLR(rst_c), 
        .E(N_347_i), .Q(\duty_cycle_r[26]_net_1 ));
    XNOR2 un1_counter_0_I_11 (.A(\counter[29]_net_1 ), .B(
        \clock_divide_r[29]_net_1 ), .Y(\DWACT_BL_EQUAL_0_E_0[10] ));
    AND2A un1_duty_cycle_r_0_I_76 (.A(\counter[25]_net_1 ), .B(
        \duty_cycle_r[25]_net_1 ), .Y(\ACT_LT3_E[2] ));
    OR2A un1_duty_cycle_r_0_I_207 (.A(\counter[9]_net_1 ), .B(
        \duty_cycle_r[9]_net_1 ), .Y(N_35));
    AO1C un1_counter_0_I_225 (.A(\clock_divide_r[1]_net_1 ), .B(
        \counter[1]_net_1 ), .C(N_18_0), .Y(N_20_0));
    OR2A un1_counter_0_I_169 (.A(\clock_divide_r[14]_net_1 ), .B(
        \counter[14]_net_1 ), .Y(N_63_0));
    DFN1E0C1 \duty_cycle_r[9]  (.D(data[1]), .CLK(GLA), .CLR(rst_c), 
        .E(duty_cycle_r_48_e_net_1), .Q(\duty_cycle_r[9]_net_1 ));
    AND3 un8_counter_I_142 (.A(\DWACT_FINC_E[28] ), .B(
        \DWACT_FINC_E[13] ), .C(\DWACT_FINC_E[16] ), .Y(N_61));
    DFN1E0C1 \clock_divide_r[3]  (.D(data[3]), .CLK(GLA), .CLR(rst_c), 
        .E(clock_divide_r_8_e_net_1), .Q(\clock_divide_r[3]_net_1 ));
    AND3 un1_duty_cycle_r_0_I_17 (.A(\DWACT_BL_EQUAL_0_E[9] ), .B(
        \DWACT_BL_EQUAL_0_E[10] ), .C(\DWACT_BL_EQUAL_0_E[11] ), .Y(
        \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E[3] ));
    OA1 un1_counter_0_I_214 (.A(I_213), .B(N_40), .C(N_39), .Y(I_214));
    AO1C un1_duty_cycle_r_0_I_53 (.A(\counter[28]_net_1 ), .B(
        \duty_cycle_r[28]_net_1 ), .C(N_134), .Y(N_136_0));
    XNOR2 un1_duty_cycle_r_0_I_35 (.A(\duty_cycle_r[29]_net_1 ), .B(
        \counter[29]_net_1 ), .Y(\DWACT_BL_EQUAL_0_E_3[2] ));
    AOI1A un1_duty_cycle_r_0_I_152 (.A(\ACT_LT4_E[0] ), .B(
        \ACT_LT4_E[1] ), .C(\ACT_LT4_E[2] ), .Y(\ACT_LT4_E[3] ));
    AND3 un1_counter_0_I_126 (.A(
        \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E_1[2] ), .B(
        \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E_4[1] ), .C(
        \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E_6[0] ), .Y(
        \DWACT_CMPLE_PO2_DWACT_COMP0_E_0[1] ));
    OR2A un1_duty_cycle_r_0_I_169 (.A(\counter[14]_net_1 ), .B(
        \duty_cycle_r[14]_net_1 ), .Y(N_63));
    DFN1C1 \counter[6]  (.D(\counter_5[6]_net_1 ), .CLK(GLA), .CLR(
        rst_c), .Q(\counter[6]_net_1 ));
    AND2 un8_counter_I_41 (.A(\counter[6]_net_1 ), .B(
        \counter[7]_net_1 ), .Y(\DWACT_FINC_E[3] ));
    XNOR2 un1_counter_0_I_122 (.A(\counter[11]_net_1 ), .B(
        \clock_divide_r[11]_net_1 ), .Y(\DWACT_BL_EQUAL_0_E_7[1] ));
    DFN1E0C1 \duty_cycle_r[29]  (.D(data[5]), .CLK(GLA), .CLR(rst_c), 
        .E(N_347_i), .Q(\duty_cycle_r[29]_net_1 ));
    DFN1C1 \counter[21]  (.D(\counter_5[21]_net_1 ), .CLK(GLA), .CLR(
        rst_c), .Q(\counter[21]_net_1 ));
    XOR2 un8_counter_I_224 (.A(N_4_0), .B(\counter[31]_net_1 ), .Y(
        I_224));
    AND2 un1_counter_0_I_20 (.A(
        \DWACT_BL_ANDTREE_0_DWACT_BL_ANDTREE_0_E_0[1] ), .B(
        \DWACT_BL_ANDTREE_0_DWACT_BL_ANDTREE_0_E_0[0] ), .Y(
        \DWACT_COMP0_E[1] ));
    AO1C un1_counter_0_I_227 (.A(\counter[2]_net_1 ), .B(
        \clock_divide_r[2]_net_1 ), .C(N_16_0), .Y(N_22_0));
    AND2 un8_counter_I_125 (.A(\counter[18]_net_1 ), .B(
        \counter[19]_net_1 ), .Y(\DWACT_FINC_E[14] ));
    XNOR2 un1_duty_cycle_r_0_I_67 (.A(\duty_cycle_r[25]_net_1 ), .B(
        \counter[25]_net_1 ), .Y(\DWACT_BL_EQUAL_0_E_2[1] ));
    AND3 un1_duty_cycle_r_0_I_125 (.A(\DWACT_BL_EQUAL_0_E[6] ), .B(
        \DWACT_BL_EQUAL_0_E[7] ), .C(\DWACT_BL_EQUAL_0_E[8] ), .Y(
        \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E[2] ));
    AND2 un1_duty_cycle_r_0_I_140 (.A(\DWACT_BL_EQUAL_0_E_0[3] ), .B(
        \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E_0[0] ), .Y(
        \DWACT_CMPLE_PO0_DWACT_COMP0_E[1] ));
    DFN1C1 \counter[3]  (.D(\counter_5[3]_net_1 ), .CLK(GLA), .CLR(
        rst_c), .Q(\counter[3]_net_1 ));
    DFN1C1 \counter[2]  (.D(\counter_5[2]_net_1 ), .CLK(GLA), .CLR(
        rst_c), .Q(\counter[2]_net_1 ));
    OR2A un1_duty_cycle_r_0_I_50 (.A(\duty_cycle_r[29]_net_1 ), .B(
        \counter[29]_net_1 ), .Y(N_133));
    DFN1E0C1 \duty_cycle_r[12]  (.D(data[4]), .CLK(GLA), .CLR(rst_c), 
        .E(duty_cycle_r_48_e_net_1), .Q(\duty_cycle_r[12]_net_1 ));
    NOR2B \counter_5[27]  (.A(I_196), .B(I_248_0), .Y(
        \counter_5[27]_net_1 ));
    AO1C un1_counter_0_I_57 (.A(\counter[30]_net_1 ), .B(
        \clock_divide_r[30]_net_1 ), .C(N_135_0), .Y(N_140_0));
    AND3 un8_counter_I_65 (.A(\DWACT_FINC_E[6] ), .B(
        \counter[9]_net_1 ), .C(\counter[10]_net_1 ), .Y(N_116));
    DFN1E0C1 \duty_cycle_r[1]  (.D(data[1]), .CLK(GLA), .CLR(rst_c), 
        .E(duty_cycle_r_40_e_net_1), .Q(\duty_cycle_r[1]_net_1 ));
    AND3 un1_counter_0_I_193 (.A(\DWACT_BL_EQUAL_0_E_5[0] ), .B(
        \DWACT_BL_EQUAL_0_E_5[1] ), .C(\DWACT_BL_EQUAL_0_E_5[2] ), .Y(
        \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E_4[0] ));
    XOR2 un8_counter_I_186 (.A(N_31), .B(\counter[26]_net_1 ), .Y(
        I_186));
    DFN1E0C1 \clock_divide_r[11]  (.D(data[3]), .CLK(GLA), .CLR(rst_c), 
        .E(N_251_i), .Q(\clock_divide_r[11]_net_1 ));
    AND2 un8_counter_I_206 (.A(\counter[27]_net_1 ), .B(
        \counter[28]_net_1 ), .Y(\DWACT_FINC_E[25] ));
    XNOR2 un1_counter_0_I_35 (.A(\counter[29]_net_1 ), .B(
        \clock_divide_r[29]_net_1 ), .Y(\DWACT_BL_EQUAL_0_E_9[2] ));
    DFN1E0C1 \clock_divide_r[16]  (.D(data[0]), .CLK(GLA), .CLR(rst_c), 
        .E(clock_divide_r_24_e_net_1), .Q(\clock_divide_r[16]_net_1 ));
    AND3 un1_duty_cycle_r_0_I_38 (.A(\DWACT_BL_EQUAL_0_E_3[0] ), .B(
        \DWACT_BL_EQUAL_0_E_3[1] ), .C(\DWACT_BL_EQUAL_0_E_3[2] ), .Y(
        \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E_2[0] ));
    DFN1E0C1 \duty_cycle_r[31]  (.D(data[7]), .CLK(GLA), .CLR(rst_c), 
        .E(N_347_i), .Q(\duty_cycle_r[31]_net_1 ));
    XNOR2 un1_duty_cycle_r_0_I_138 (.A(\duty_cycle_r[18]_net_1 ), .B(
        \counter[18]_net_1 ), .Y(\DWACT_BL_EQUAL_0_E_0[3] ));
    XNOR2 un1_duty_cycle_r_0_I_120 (.A(\duty_cycle_r[16]_net_1 ), .B(
        \counter[16]_net_1 ), .Y(\DWACT_BL_EQUAL_0_E[6] ));
    OR2 duty_cycle_r_40_e (.A(N_261), .B(un1_duty_cycle_r34_net_1), .Y(
        duty_cycle_r_40_e_net_1));