top.v

Core_PWM,verilog语言编写

`timescale 1 ns/100 ps
// Version: 8.0 SP1 8.0.1.13


module PWM(
       data,
       addr,
       rst_c,
       GLA,
       pwmout_c,
       N_261,
       WE,
       CS,
       N_108
    );
input  [7:0] data;
input  [2:0] addr;
input  rst_c;
input  GLA;
output pwmout_c;
input  N_261;
input  WE;
input  CS;
input  N_108;

    wire I_248, \DWACT_COMP0_E[1] , I_243, \DWACT_COMP0_E[0] , 
        \counter_5[0]_net_1 , \counter[0]_net_1 , \counter_5[1]_net_1 , 
        I_5, \counter_5[2]_net_1 , I_9, \counter_5[3]_net_1 , I_13_0, 
        \counter_5[4]_net_1 , I_20, \counter_5[5]_net_1 , I_24, 
        \counter_5[6]_net_1 , I_31, \counter_5[7]_net_1 , I_38, 
        \counter_5[8]_net_1 , I_45, \counter_5[9]_net_1 , I_52, I_204, 
        \clock_divide_r[6]_net_1 , \counter[6]_net_1 , I_210, 
        \counter[7]_net_1 , \clock_divide_r[7]_net_1 , I_213, N_36, 
        N_37, I_214, N_40, N_39, I_238, 
        \DWACT_CMPLE_PO2_DWACT_COMP0_E[1] , 
        \DWACT_CMPLE_PO2_DWACT_COMP0_E[2] , 
        \DWACT_CMPLE_PO2_DWACT_COMP0_E_0[1] , 
        \DWACT_CMPLE_PO2_DWACT_COMP0_E[0] , \counter_5[10]_net_1 , 
        I_56, I_248_1, \counter_5[11]_net_1 , I_66, 
        \counter_5[12]_net_1 , I_73, \counter_5[13]_net_1 , I_77, 
        \counter_5[14]_net_1 , I_84, \counter_5[15]_net_1 , I_91, 
        \counter_5[16]_net_1 , I_98, \counter_5[17]_net_1 , I_105, 
        \counter_5[18]_net_1 , I_115, \counter_5[19]_net_1 , I_122, 
        \counter_5[20]_net_1 , I_129, \counter_5[21]_net_1 , I_136, 
        I_248_0, \counter_5[22]_net_1 , I_143, \counter_5[23]_net_1 , 
        I_156, \counter_5[24]_net_1 , I_166, \counter_5[25]_net_1 , 
        I_173, \counter_5[26]_net_1 , I_186, \counter_5[27]_net_1 , 
        I_196, \counter_5[28]_net_1 , I_203, \counter_5[29]_net_1 , 
        I_210_0, \counter_5[30]_net_1 , I_217, \counter_5[31]_net_1 , 
        I_224, N_157, \counter[1]_net_1 , N_149, \counter[3]_net_1 , 
        \DWACT_FINC_E[0] , N_126, \counter[8]_net_1 , 
        \DWACT_FINC_E[4] , N_111, \DWACT_FINC_E[7] , \DWACT_FINC_E[6] , 
        duty_cycle_r_48_e_0_net_1, un1_duty_cycle_r34_net_1, N_251_i, 
        un1_duty_cycle_r34_1_net_1, duty_cycle_r_48_e_net_1, 
        clock_divide_r_8_e_net_1, clock_divide_r_24_e_net_1, N_283_i, 
        duty_cycle_r_40_e_net_1, duty_cycle_r_56_e_net_1, N_347_i, 
        un1_duty_cycle_r_i, \clock_divide_r[0]_net_1 , 
        \clock_divide_r[1]_net_1 , \clock_divide_r[2]_net_1 , 
        \clock_divide_r[3]_net_1 , \clock_divide_r[4]_net_1 , 
        \clock_divide_r[5]_net_1 , \clock_divide_r[8]_net_1 , 
        \clock_divide_r[9]_net_1 , \clock_divide_r[10]_net_1 , 
        \clock_divide_r[11]_net_1 , \clock_divide_r[12]_net_1 , 
        \clock_divide_r[13]_net_1 , \clock_divide_r[14]_net_1 , 
        \clock_divide_r[15]_net_1 , \clock_divide_r[16]_net_1 , 
        \clock_divide_r[17]_net_1 , \clock_divide_r[18]_net_1 , 
        \clock_divide_r[19]_net_1 , \clock_divide_r[20]_net_1 , 
        \clock_divide_r[21]_net_1 , \clock_divide_r[22]_net_1 , 
        \clock_divide_r[23]_net_1 , \clock_divide_r[24]_net_1 , 
        \clock_divide_r[25]_net_1 , \clock_divide_r[26]_net_1 , 
        \clock_divide_r[27]_net_1 , \clock_divide_r[28]_net_1 , 
        \clock_divide_r[29]_net_1 , \clock_divide_r[30]_net_1 , 
        \clock_divide_r[31]_net_1 , \duty_cycle_r[0]_net_1 , 
        \duty_cycle_r[1]_net_1 , \duty_cycle_r[2]_net_1 , 
        \duty_cycle_r[3]_net_1 , \duty_cycle_r[4]_net_1 , 
        \duty_cycle_r[5]_net_1 , \duty_cycle_r[6]_net_1 , 
        \duty_cycle_r[7]_net_1 , \duty_cycle_r[8]_net_1 , 
        \duty_cycle_r[9]_net_1 , \duty_cycle_r[10]_net_1 , 
        \duty_cycle_r[11]_net_1 , \duty_cycle_r[12]_net_1 , 
        \duty_cycle_r[13]_net_1 , \duty_cycle_r[14]_net_1 , 
        \duty_cycle_r[15]_net_1 , \duty_cycle_r[16]_net_1 , 
        \duty_cycle_r[17]_net_1 , \duty_cycle_r[18]_net_1 , 
        \duty_cycle_r[19]_net_1 , \duty_cycle_r[20]_net_1 , 
        \duty_cycle_r[21]_net_1 , \duty_cycle_r[22]_net_1 , 
        \duty_cycle_r[23]_net_1 , \duty_cycle_r[24]_net_1 , 
        \duty_cycle_r[25]_net_1 , \duty_cycle_r[26]_net_1 , 
        \duty_cycle_r[27]_net_1 , \duty_cycle_r[28]_net_1 , 
        \duty_cycle_r[29]_net_1 , \duty_cycle_r[30]_net_1 , 
        \duty_cycle_r[31]_net_1 , \counter[2]_net_1 , 
        \counter[4]_net_1 , \counter[5]_net_1 , \counter[9]_net_1 , 
        \counter[10]_net_1 , \counter[11]_net_1 , \counter[12]_net_1 , 
        \counter[13]_net_1 , \counter[14]_net_1 , \counter[15]_net_1 , 
        \counter[16]_net_1 , \counter[17]_net_1 , \counter[18]_net_1 , 
        \counter[19]_net_1 , \counter[20]_net_1 , \counter[21]_net_1 , 
        \counter[22]_net_1 , \counter[23]_net_1 , \counter[24]_net_1 , 
        \counter[25]_net_1 , \counter[26]_net_1 , \counter[27]_net_1 , 
        \counter[28]_net_1 , \counter[29]_net_1 , \counter[30]_net_1 , 
        \counter[31]_net_1 , N_4_0, \DWACT_FINC_E[24] , 
        \DWACT_FINC_E[23] , \DWACT_FINC_E[27] , \DWACT_FINC_E[26] , 
        N_9, N_14, \DWACT_FINC_E[25] , N_19, \DWACT_FINC_E[29] , 
        \DWACT_FINC_E[30] , N_24, \DWACT_FINC_E[15] , 
        \DWACT_FINC_E[17] , \DWACT_FINC_E[22] , N_31, 
        \DWACT_FINC_E[21] , \DWACT_FINC_E[9] , \DWACT_FINC_E[12] , 
        \DWACT_FINC_E[20] , N_40_0, \DWACT_FINC_E[13] , 
        \DWACT_FINC_E[19] , N_45, \DWACT_FINC_E[18] , N_52, 
        \DWACT_FINC_E[33] , \DWACT_FINC_E[34] , \DWACT_FINC_E[2] , 
        \DWACT_FINC_E[5] , N_61, \DWACT_FINC_E[28] , 
        \DWACT_FINC_E[16] , N_66, N_71, \DWACT_FINC_E[14] , N_76, N_81, 
        \DWACT_FINC_E[10] , N_88, \DWACT_FINC_E[11] , N_93, N_98, 
        N_103, \DWACT_FINC_E[8] , N_108_0, N_116, N_123, 
        \DWACT_FINC_E[3] , N_131, N_136, N_141, \DWACT_FINC_E[1] , 
        N_146, N_154, \DWACT_COMP0_E[2] , \DWACT_COMP0_E_0[1] , 
        \DWACT_COMP0_E_0[0] , \DWACT_CMPLE_PO2_DWACT_COMP0_E_1[1] , 
        \DWACT_CMPLE_PO2_DWACT_COMP0_E_0[2] , 
        \DWACT_CMPLE_PO2_DWACT_COMP0_E_0[0] , 
        \DWACT_CMPLE_PO2_DWACT_COMP0_E_2[1] , 
        \DWACT_CMPLE_PO2_DWACT_COMP0_E_1[2] , 
        \DWACT_CMPLE_PO2_DWACT_COMP0_E_1[0] , N_25, N_24_0, N_23, N_20, 
        N_22, N_21, N_19_0, N_16, N_17, N_18, N_41, N_40_1, N_39_0, 
        N_36_0, N_38, N_37_0, N_35, N_32, N_33, N_34, 
        \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E[1] , 
        \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E[0] , \DWACT_BL_EQUAL_0_E[4] , 
        \DWACT_BL_EQUAL_0_E[3] , \DWACT_BL_EQUAL_0_E[0] , 
        \DWACT_BL_EQUAL_0_E[1] , \DWACT_BL_EQUAL_0_E[2] , 
        \DWACT_CMPLE_PO0_DWACT_COMP0_E[1] , 
        \DWACT_CMPLE_PO0_DWACT_COMP0_E[2] , 
        \DWACT_CMPLE_PO0_DWACT_COMP0_E[0] , N_69, N_68, N_67, N_64, 
        N_66_0, N_65, N_63, N_60, N_61_0, N_62, \ACT_LT4_E[3] , 
        \ACT_LT4_E[6] , \ACT_LT4_E[10] , \ACT_LT4_E[7] , 
        \ACT_LT4_E[8] , \ACT_LT4_E[5] , \ACT_LT4_E[4] , \ACT_LT4_E[0] , 
        \ACT_LT4_E[1] , \ACT_LT4_E[2] , \DWACT_BL_EQUAL_0_E_0[3] , 
        \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E_0[0] , 
        \DWACT_BL_EQUAL_0_E_0[0] , \DWACT_BL_EQUAL_0_E_0[1] , 
        \DWACT_BL_EQUAL_0_E_0[2] , 
        \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E[2] , 
        \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E_0[1] , 
        \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E_1[0] , 
        \DWACT_BL_EQUAL_0_E[6] , \DWACT_BL_EQUAL_0_E[7] , 
        \DWACT_BL_EQUAL_0_E[8] , \DWACT_BL_EQUAL_0_E_1[3] , 
        \DWACT_BL_EQUAL_0_E_0[4] , \DWACT_BL_EQUAL_0_E[5] , 
        \DWACT_BL_EQUAL_0_E_1[0] , \DWACT_BL_EQUAL_0_E_1[1] , 
        \DWACT_BL_EQUAL_0_E_1[2] , 
        \DWACT_CMPLE_PO0_DWACT_COMP0_E_0[1] , 
        \DWACT_CMPLE_PO0_DWACT_COMP0_E_0[2] , 
        \DWACT_CMPLE_PO0_DWACT_COMP0_E_0[0] , 
        \DWACT_CMPLE_PO2_DWACT_COMP0_E_3[1] , 
        \DWACT_CMPLE_PO2_DWACT_COMP0_E_2[2] , 
        \DWACT_CMPLE_PO2_DWACT_COMP0_E_2[0] , N_115, N_114, N_113, 
        N_110, N_112, N_111_0, N_109, N_106, N_107, N_108_1, 
        \ACT_LT3_E[3] , \ACT_LT3_E[4] , \ACT_LT3_E[5] , \ACT_LT3_E[0] , 
        \ACT_LT3_E[1] , \ACT_LT3_E[2] , \DWACT_BL_EQUAL_0_E_2[2] , 
        \DWACT_BL_EQUAL_0_E_2[1] , \DWACT_BL_EQUAL_0_E_2[0] , N_141_0, 
        N_140, N_139, N_136_0, N_138, N_137, N_135, N_132, N_133, 
        N_134, \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E_1[1] , 
        \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E_2[0] , 
        \DWACT_BL_EQUAL_0_E_1[4] , \DWACT_BL_EQUAL_0_E_2[3] , 
        \DWACT_BL_EQUAL_0_E_3[0] , \DWACT_BL_EQUAL_0_E_3[1] , 
        \DWACT_BL_EQUAL_0_E_3[2] , 
        \DWACT_BL_ANDTREE_0_DWACT_BL_ANDTREE_0_E[1] , 
        \DWACT_BL_ANDTREE_0_DWACT_BL_ANDTREE_0_E[0] , 
        \DWACT_BL_EQUAL_0_E[12] , 
        \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E[3] , 
        \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E_3[0] , 
        \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E_2[1] , 
        \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E_0[2] , 
        \DWACT_BL_EQUAL_0_E[9] , \DWACT_BL_EQUAL_0_E[10] , 
        \DWACT_BL_EQUAL_0_E[11] , \DWACT_BL_EQUAL_0_E_0[6] , 
        \DWACT_BL_EQUAL_0_E_0[7] , \DWACT_BL_EQUAL_0_E_0[8] , 
        \DWACT_BL_EQUAL_0_E_3[3] , \DWACT_BL_EQUAL_0_E_2[4] , 
        \DWACT_BL_EQUAL_0_E_0[5] , \DWACT_BL_EQUAL_0_E_4[0] , 
        \DWACT_BL_EQUAL_0_E_4[1] , \DWACT_BL_EQUAL_0_E_4[2] , N_25_0, 
        N_24_1, N_23_0, N_20_0, N_22_0, N_21_0, N_19_1, N_16_0, N_17_0, 
        N_18_0, N_35_0, N_33_0, N_34_0, 
        \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E_3[1] , 
        \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E_4[0] , 
        \DWACT_BL_EQUAL_0_E_3[4] , \DWACT_BL_EQUAL_0_E_4[3] , 
        \DWACT_BL_EQUAL_0_E_5[0] , \DWACT_BL_EQUAL_0_E_5[1] , 
        \DWACT_BL_EQUAL_0_E_5[2] , 
        \DWACT_CMPLE_PO0_DWACT_COMP0_E_1[1] , 
        \DWACT_CMPLE_PO0_DWACT_COMP0_E_1[2] , 
        \DWACT_CMPLE_PO0_DWACT_COMP0_E_1[0] , N_69_0, N_68_0, N_67_0, 
        N_64_0, N_66_1, N_65_0, N_63_0, N_60_0, N_61_1, N_62_0, 
        \ACT_LT4_E_0[3] , \ACT_LT4_E_0[6] , \ACT_LT4_E_0[10] , 
        \ACT_LT4_E_0[7] , \ACT_LT4_E_0[8] , \ACT_LT4_E_0[5] , 
        \ACT_LT4_E_0[4] , \ACT_LT4_E_0[0] , \ACT_LT4_E_0[1] , 
        \ACT_LT4_E_0[2] , \DWACT_BL_EQUAL_0_E_5[3] , 
        \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E_5[0] , 
        \DWACT_BL_EQUAL_0_E_6[0] , \DWACT_BL_EQUAL_0_E_6[1] , 
        \DWACT_BL_EQUAL_0_E_6[2] , 
        \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E_1[2] , 
        \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E_4[1] , 
        \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E_6[0] , 
        \DWACT_BL_EQUAL_0_E_1[6] , \DWACT_BL_EQUAL_0_E_1[7] , 
        \DWACT_BL_EQUAL_0_E_1[8] , \DWACT_BL_EQUAL_0_E_6[3] , 
        \DWACT_BL_EQUAL_0_E_4[4] , \DWACT_BL_EQUAL_0_E_1[5] , 
        \DWACT_BL_EQUAL_0_E_7[0] , \DWACT_BL_EQUAL_0_E_7[1] , 
        \DWACT_BL_EQUAL_0_E_7[2] , 
        \DWACT_CMPLE_PO0_DWACT_COMP0_E_2[1] , 
        \DWACT_CMPLE_PO0_DWACT_COMP0_E_2[2] , 
        \DWACT_CMPLE_PO0_DWACT_COMP0_E_2[0] , 
        \DWACT_CMPLE_PO2_DWACT_COMP0_E_4[1] , 
        \DWACT_CMPLE_PO2_DWACT_COMP0_E_3[2] , 
        \DWACT_CMPLE_PO2_DWACT_COMP0_E_3[0] , N_115_0, N_114_0, 
        N_113_0, N_110_0, N_112_0, N_111_1, N_109_0, N_106_0, N_107_0, 
        N_108_2, \ACT_LT3_E_0[3] , \ACT_LT3_E_0[4] , \ACT_LT3_E_0[5] , 
        \ACT_LT3_E_0[0] , \ACT_LT3_E_0[1] , \ACT_LT3_E_0[2] , 
        \DWACT_BL_EQUAL_0_E_8[2] , \DWACT_BL_EQUAL_0_E_8[1] , 
        \DWACT_BL_EQUAL_0_E_8[0] , N_141_1, N_140_0, N_139_0, N_136_1, 
        N_138_0, N_137_0, N_135_0, N_132_0, N_133_0, N_134_0, 
        \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E_5[1] , 
        \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E_7[0] , 
        \DWACT_BL_EQUAL_0_E_5[4] , \DWACT_BL_EQUAL_0_E_7[3] , 
        \DWACT_BL_EQUAL_0_E_9[0] , \DWACT_BL_EQUAL_0_E_9[1] , 
        \DWACT_BL_EQUAL_0_E_9[2] , 
        \DWACT_BL_ANDTREE_0_DWACT_BL_ANDTREE_0_E_0[1] , 
        \DWACT_BL_ANDTREE_0_DWACT_BL_ANDTREE_0_E_0[0] , 
        \DWACT_BL_EQUAL_0_E_0[12] , 
        \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E_0[3] , 
        \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E_8[0] , 
        \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E_6[1] , 
        \DWACT_BL_EQUAL_0_DWACT_ANDTREE_E_2[2] , 
        \DWACT_BL_EQUAL_0_E_0[9] , \DWACT_BL_EQUAL_0_E_0[10] , 
        \DWACT_BL_EQUAL_0_E_0[11] , \DWACT_BL_EQUAL_0_E_2[6] , 
        \DWACT_BL_EQUAL_0_E_2[7] , \DWACT_BL_EQUAL_0_E_2[8] , 
        \DWACT_BL_EQUAL_0_E_8[3] , \DWACT_BL_EQUAL_0_E_6[4] , 
        \DWACT_BL_EQUAL_0_E_2[5] , \DWACT_BL_EQUAL_0_E_10[0] , 
        \DWACT_BL_EQUAL_0_E_10[1] , \DWACT_BL_EQUAL_0_E_10[2] , GND, 
        VCC, GND_net_1, VCC_net_1;