top.srd

Core_PWM,verilog语言编写

f "noname"; #file 0
f "d:\libero\synplify\synplify_862h\lib\proasic\fusion.v"; #file 1
f "c:\actelprj\pwm\hdl\pwm.v"; #file 2
f "c:\actelprj\pwm\hdl\pwm_contr.v"; #file 3
f "c:\actelprj\pwm\smartgen\pll_1\pll_1.v"; #file 4
f "c:\actelprj\pwm\hdl\top.v"; #file 5
f ""; #file 6
VNAME 'work.PWM.verilog'; # view id 0
VNAME 'work.PLL_1.verilog'; # view id 1
VNAME 'work.control.verilog'; # view id 2
VNAME 'work.top.verilog'; # view id 3
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