control.srr
来自「Core_PWM,verilog语言编写」· SRR 代码 · 共 559 行 · 第 1/3 页
SRR
559 行
Clock
---------------------------------------------------------------------------------------------------
bit1[2] control|count_inferred_clock[21] DFN1C1 D bit0[2] 9.590 8.378
bit2[2] control|count_inferred_clock[21] DFN1C1 D bit1[2] 9.590 8.378
bit1[0] control|count_inferred_clock[21] DFN1C1 D bit0[0] 9.590 8.587
bit1[1] control|count_inferred_clock[21] DFN1C1 D bit0[1] 9.590 8.587
bit2[0] control|count_inferred_clock[21] DFN1C1 D bit1[0] 9.590 8.587
bit2[1] control|count_inferred_clock[21] DFN1C1 D bit1[1] 9.590 8.587
===================================================================================================
Worst Path Information
***********************
Path information for path number 1:
Requested Period: 10.000
- Setup time: 0.410
= Required time: 9.590
- Propagation time: 1.212
= Slack (non-critical) : 8.378
Number of logic level(s): 0
Starting point: bit0[2] / Q
Ending point: bit1[2] / D
The start point is clocked by control|count_inferred_clock[21] [rising] on pin CLK
The end point is clocked by control|count_inferred_clock[21] [rising] on pin CLK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-------------------------------------------------------------------------------
bit0[2] DFN1C1 Q Out 0.476 0.476 -
bit0[2] Net - - 0.736 - 3
bit1[2] DFN1C1 D In - 1.212 -
===============================================================================
Total path delay (propagation time + setup) of 1.622 is 0.886(54.6%) logic and 0.736(45.4%) route.
====================================
Detailed Report for Clock: control|count_inferred_clock[23]
====================================
Starting Points with Worst Slack
********************************
Starting Arrival
Instance Reference Type Pin Net Time Slack
Clock
---------------------------------------------------------------------------------------------------
data0[0] control|count_inferred_clock[23] DFN1P1 Q data0[0] 0.476 1.920
data1[0] control|count_inferred_clock[23] DFN1P1 Q data1[0] 0.476 1.920
data2[0] control|count_inferred_clock[23] DFN1C1 Q data2[0] 0.476 1.920
data3[0] control|count_inferred_clock[23] DFN1C1 Q data3[0] 0.476 1.920
data4[0] control|count_inferred_clock[23] DFN1P1 Q data4[0] 0.476 1.920
data5[0] control|count_inferred_clock[23] DFN1P1 Q data5[0] 0.476 1.920
data6[0] control|count_inferred_clock[23] DFN1C1 Q data6[0] 0.476 1.920
data7[0] control|count_inferred_clock[23] DFN1C1 Q data7[0] 0.476 1.920
data0[2] control|count_inferred_clock[23] DFN1P1 Q data0[2] 0.476 2.817
data1[2] control|count_inferred_clock[23] DFN1P1 Q data1[2] 0.476 2.817
===================================================================================================
Ending Points with Worst Slack
******************************
Starting Required
Instance Reference Type Pin Net Time Slack
Clock
-----------------------------------------------------------------------------------------------------------------------
data0[7] control|count_inferred_clock[23] DFN1C1 D ADD_8x8_medium_area_I30_Y_6 9.590 1.920
data1[7] control|count_inferred_clock[23] DFN1C1 D ADD_8x8_medium_area_I30_Y_4 9.590 1.920
data2[7] control|count_inferred_clock[23] DFN1C1 D ADD_8x8_medium_area_I30_Y_3 9.590 1.920
data3[7] control|count_inferred_clock[23] DFN1C1 D ADD_8x8_medium_area_I30_Y_2 9.590 1.920
data4[7] control|count_inferred_clock[23] DFN1P1 D ADD_8x8_medium_area_I30_Y_1 9.590 1.920
data5[7] control|count_inferred_clock[23] DFN1C1 D ADD_8x8_medium_area_I30_Y_0 9.590 1.920
data6[7] control|count_inferred_clock[23] DFN1C1 D ADD_8x8_medium_area_I30_Y 9.590 1.920
data7[7] control|count_inferred_clock[23] DFN1C1 D ADD_8x8_medium_area_I30_Y_5 9.590 1.920
data0[5] control|count_inferred_clock[23] DFN1C1 D ADD_8x8_medium_area_I28_Y_6 9.590 2.821
data1[5] control|count_inferred_clock[23] DFN1P1 D ADD_8x8_medium_area_I28_Y_4 9.590 2.821
=======================================================================================================================
Worst Path Information
***********************
Path information for path number 1:
Requested Period: 10.000
- Setup time: 0.410
= Required time: 9.590
- Propagation time: 7.670
= Slack (critical) : 1.920
Number of logic level(s): 6
Starting point: data0[0] / Q
Ending point: data0[7] / D
The start point is clocked by control|count_inferred_clock[23] [rising] on pin CLK
The end point is clocked by control|count_inferred_clock[23] [rising] on pin CLK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-----------------------------------------------------------------------------------------------------
data0[0] DFN1P1 Q Out 0.476 0.476 -
data0[0] Net - - 0.736 - 3
un1_data0.ADD_8x8_medium_area_I0_CO1 NOR3A A In - 1.212 -
un1_data0.ADD_8x8_medium_area_I0_CO1 NOR3A Y Out 0.483 1.695 -
un1_data0.N116 Net - - 0.527 - 2
un1_data0.ADD_8x8_medium_area_I12_Y AO13 B In - 2.222 -
un1_data0.ADD_8x8_medium_area_I12_Y AO13 Y Out 0.677 2.899 -
un1_data0.N135 Net - - 0.736 - 3
un1_data0.ADD_8x8_medium_area_I13_Y AO1B A In - 3.634 -
un1_data0.ADD_8x8_medium_area_I13_Y AO1B Y Out 0.374 4.009 -
un1_data0.N145 Net - - 0.736 - 3
un1_data0.ADD_8x8_medium_area_I20_Y AO1B A In - 4.744 -
un1_data0.ADD_8x8_medium_area_I20_Y AO1B Y Out 0.374 5.119 -
un1_data0.N147 Net - - 0.527 - 2
un1_data0.ADD_8x8_medium_area_I21_Y AO13 B In - 5.646 -
un1_data0.ADD_8x8_medium_area_I21_Y AO13 Y Out 0.677 6.322 -
un1_data0.N149 Net - - 0.313 - 1
un1_data0.ADD_8x8_medium_area_I30_Y XNOR3 C In - 6.636 -
un1_data0.ADD_8x8_medium_area_I30_Y XNOR3 Y Out 0.721 7.357 -
ADD_8x8_medium_area_I30_Y_6 Net - - 0.313 - 1
data0[7] DFN1C1 D In - 7.670 -
=====================================================================================================
Total path delay (propagation time + setup) of 8.080 is 4.193(51.9%) logic and 3.887(48.1%) route.
##### END OF TIMING REPORT #####]
--------------------------------------------------------------------------------
Report for cell control.verilog
Core Cell usage:
cell count area count*area
DFN1C1 99 1.0 99.0
MX2 56 1.0 56.0
XNOR3 56 1.0 56.0
AND3 32 1.0 32.0
AO13 32 1.0 32.0
XOR2 26 1.0 26.0
AO1D 17 1.0 17.0
ZOR3 16 1.0 16.0
AO1B 16 1.0 16.0
DFN1P1 15 1.0 15.0
OR3A 8 1.0 8.0
AX1B 8 1.0 8.0
AND2 8 1.0 8.0
OR3B 8 1.0 8.0
NOR3A 8 1.0 8.0
NOR2B 5 1.0 5.0
NOR3C 4 1.0 4.0
BUFF 2 1.0 2.0
OR2A 2 1.0 2.0
CLKINT 1 0.0 0.0
OR2 1 1.0 1.0
OR2B 1 1.0 1.0
INV 1 1.0 1.0
OAI1 1 1.0 1.0
VCC 1 0.0 0.0
GND 1 0.0 0.0
----- ----------
TOTAL 425 422.0
IO Cell usage:
cell count
OUTBUF 14
INBUF 4
CLKBUF 1
-----
TOTAL 19
Mapper successful!
Process took 0h:00m:06s realtime, 0h:00m:05s cputime
# Tue Sep 25 08:33:13 2007
###########################################################]
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