control.srr

Core_PWM,verilog语言编写

#Build: Synplify Pro 8.6.2H, Build 017R, Dec  7 2006
#install: D:\Libero\Synplify\Synplify_862H
#OS: Windows XP 5.1
#Hostname: SHOUJINQIAO

#Tue Sep 25 08:33:03 2007

$ Start of Compile
#Tue Sep 25 08:33:03 2007

Synplicity Verilog Compiler, version 3.7, Build 090R, built Nov 17 2006
Copyright (C) 1994-2006, Synplicity Inc.  All Rights Reserved

@I::"D:\Libero\Synplify\Synplify_862H\lib\proasic\fusion.v"
@I::"C:\Actelprj\PWM\hdl\PWM_contr.v"
Verilog syntax check successful!
Selecting top level module control
@N: CG364 :"C:\Actelprj\PWM\hdl\PWM_contr.v":2:7:2:13|Synthesizing module control

@END
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Tue Sep 25 08:33:04 2007

###########################################################]
Synplicity Proasic Technology Mapper, Version 9.0.0, Build 368R, Built Nov 27 2006 12:29:38
Copyright (C) 1994-2006, Synplicity Inc.  All Rights Reserved
Product Version Version 8.6.2H
@N: MF249 |Running in 32-bit mode.
@N: MF258 |Gated clock conversion disabled 
@W: BN153 |View "prim", Cell "NGMUX", Port "CLK0": remove clock marking
@W: BN153 |View "prim", Cell "NGMUX", Port "CLK1": remove clock marking
@W: BN154 |View "prim" of Cell "NGMUX": 4 sequential timing arcs are removed


RTL optimization done.

Finished RTL optimizations (Time elapsed 0h:00m:00s; Memory used current: 43MB peak: 45MB)
@N: MF176 |Default generator successful 
@N: MF176 |Default generator successful 
@N: MF176 |Default generator successful 
@N: MF176 |Default generator successful 
@N: MF176 |Default generator successful 
@N: MF176 |Default generator successful 
@N: MF238 :"c:\actelprj\pwm\hdl\pwm_contr.v":27:17:27:30|Found 24 bit incrementor, 'un3_count[23:0]'
@N: MF176 |Default generator successful 
@N: MF176 |Default generator successful 

Finished factoring (Time elapsed 0h:00m:02s; Memory used current: 44MB peak: 45MB)

Finished gated-clock and generated-clock conversion (Time elapsed 0h:00m:02s; Memory used current: 44MB peak: 45MB)

Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:02s; Memory used current: 45MB peak: 46MB)

Starting Early Timing Optimization (Time elapsed 0h:00m:03s; Memory used current: 45MB peak: 47MB)

Finished Early Timing Optimization (Time elapsed 0h:00m:03s; Memory used current: 45MB peak: 47MB)

Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:03s; Memory used current: 45MB peak: 47MB)

Finished preparing to map (Time elapsed 0h:00m:04s; Memory used current: 47MB peak: 47MB)

High Fanout Net Report
**********************

Driver Instance / Pin Name     Fanout, notes                   
---------------------------------------------------------------
rst_pad / Y                    108 : 108 asynchronous set/reset
addr_1[0] / Q                  22                              
addr_1[1] / Q                  24                              
addr_1[2] / Q                  39                              
data7_1_sqmuxa_i_0 / Y         15                              
data3_1_sqmuxa_i_0 / Y         15                              
data4_1_sqmuxa_i_0 / Y         15                              
data0_0_sqmuxa_1_i / Y         15                              
data5_1_sqmuxa_i_0 / Y         15                              
data2_1_sqmuxa_i_0 / Y         15                              
data6_1_sqmuxa_i_0 / Y         15                              
data1_1_sqmuxa_i_0 / Y         15                              
===============================================================

Promoting Net count[23] on CLKINT  count_inferred_clock[23]
Promoting Net rst_c on CLKBUF  rst_pad
Replicating N_8, fanout 15 segments 2
Replicating N_18, fanout 15 segments 2
Replicating N_10, fanout 15 segments 2
Replicating N_16, fanout 15 segments 2
Replicating N_6, fanout 15 segments 2
Replicating N_14, fanout 15 segments 2
Replicating N_12, fanout 15 segments 2
Replicating N_4, fanout 15 segments 2
Replicating LED_c_c[2], fanout 39 segments 4
Replicating LED_c_c[1], fanout 24 segments 2
Replicating LED_c_c[0], fanout 30 segments 3
Buffering CLK48M_c, fanout 32 segments 3
Replicating key_buf[2], fanout 18 segments 2

Finished technology mapping (Time elapsed 0h:00m:04s; Memory used current: 47MB peak: 49MB)

Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:04s; Memory used current: 47MB peak: 49MB)

Added 2 Buffers
Added 15 Cells via replication

Finished restoring hierarchy (Time elapsed 0h:00m:04s; Memory used current: 47MB peak: 49MB)
Writing Analyst data base C:\Actelprj\PWM\synthesis\control.srm
@N: BN225 |Writing default property annotation file C:\Actelprj\PWM\synthesis\control.map.
Writing EDIF Netlist and constraint files
Found clock control|CLK48M with period 10.00ns 
Found clock control|count_inferred_clock[23] with period 10.00ns 
Found clock control|count_inferred_clock[20] with period 10.00ns 
Found clock control|count_inferred_clock[21] with period 10.00ns 


##### START OF TIMING REPORT #####[
# Timing Report written on Tue Sep 25 08:33:13 2007
#


Top view:               control
Library name:           fusion
Operating conditions:   COMWC-2 ( T = 70.0, V = 1.58, P = 1.15, tree_type = balanced_tree )
Requested Frequency:    100.0 MHz
Wire load mode:         top
Wire load model:        fusion
Paths requested:        5
Constraint File(s):    
@N: MT195 |This timing report estimates place and route data. Please look at the place and route timing report for final timing..

@N: MT197 |Clock constraints cover only FF-to-FF paths associated with the clock..



Performance Summary 
*******************


Worst slack in design: 1.920

                                     Requested     Estimated     Requested     Estimated               Clock        Clock              
Starting Clock                       Frequency     Frequency     Period        Period        Slack     Type         Group              
---------------------------------------------------------------------------------------------------------------------------------------
control|CLK48M                       100.0 MHz     133.0 MHz     10.000        7.521         2.479     inferred     Inferred_clkgroup_0
control|count_inferred_clock[20]     100.0 MHz     166.6 MHz     10.000        6.002         3.998     inferred     Inferred_clkgroup_2
control|count_inferred_clock[21]     100.0 MHz     616.5 MHz     10.000        1.622         8.378     inferred     Inferred_clkgroup_1
control|count_inferred_clock[23]     100.0 MHz     123.8 MHz     10.000        8.080         1.920     inferred     Inferred_clkgroup_3
=======================================================================================================================================





Clock Relationships
*******************

Clocks                                                              |    rise  to  rise   |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
----------------------------------------------------------------------------------------------------------------------------------------------------------
Starting                          Ending                            |  constraint  slack  |  constraint  slack  |  constraint  slack  |  constraint  slack
----------------------------------------------------------------------------------------------------------------------------------------------------------
control|CLK48M                    control|CLK48M                    |  10.000      2.479  |  No paths    -      |  No paths    -      |  No paths    -    
control|count_inferred_clock[21]  control|count_inferred_clock[21]  |  10.000      8.378  |  No paths    -      |  No paths    -      |  No paths    -    
control|count_inferred_clock[21]  control|count_inferred_clock[20]  |  Diff grp    -      |  No paths    -      |  No paths    -      |  No paths    -    
control|count_inferred_clock[21]  control|count_inferred_clock[23]  |  Diff grp    -      |  No paths    -      |  No paths    -      |  No paths    -    
control|count_inferred_clock[20]  control|CLK48M                    |  Diff grp    -      |  No paths    -      |  No paths    -      |  No paths    -    
control|count_inferred_clock[20]  control|count_inferred_clock[20]  |  10.000      3.998  |  No paths    -      |  No paths    -      |  No paths    -    
control|count_inferred_clock[20]  control|count_inferred_clock[23]  |  Diff grp    -      |  No paths    -      |  No paths    -      |  No paths    -    
control|count_inferred_clock[23]  control|CLK48M                    |  Diff grp    -      |  No paths    -      |  No paths    -      |  No paths    -    
control|count_inferred_clock[23]  control|count_inferred_clock[23]  |  10.000      1.920  |  No paths    -      |  No paths    -      |  No paths    -    
==========================================================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************

		No IO constraint found 



====================================
Detailed Report for Clock: control|CLK48M
====================================



Starting Points with Worst Slack