top.tlg

Core_PWM,verilog语言编写

Selecting top level module top
@N: CG364 :"C:\Actelprj\PWM\hdl\PWM.v":2:7:2:9|Synthesizing module PWM

@N: CG364 :"D:\Libero\Synplify\Synplify_862H\lib\proasic\fusion.v":2043:7:2043:9|Synthesizing module VCC

@N: CG364 :"D:\Libero\Synplify\Synplify_862H\lib\proasic\fusion.v":1224:7:1224:9|Synthesizing module GND

@N: CG364 :"D:\Libero\Synplify\Synplify_862H\lib\proasic\fusion.v":2974:7:2974:9|Synthesizing module PLL

@N: CG364 :"D:\Libero\Synplify\Synplify_862H\lib\proasic\fusion.v":260:7:260:12|Synthesizing module PLLINT

@N: CG364 :"C:\Actelprj\PWM\smartgen\PLL_1\PLL_1.v":5:7:5:11|Synthesizing module PLL_1

@N: CG364 :"C:\Actelprj\PWM\hdl\PWM_contr.v":2:7:2:13|Synthesizing module control

@W: CG133 :"C:\Actelprj\PWM\hdl\PWM_contr.v":15:12:15:15|No assignment to bit0
@W: CG133 :"C:\Actelprj\PWM\hdl\PWM_contr.v":15:17:15:20|No assignment to bit1
@W: CG133 :"C:\Actelprj\PWM\hdl\PWM_contr.v":15:22:15:25|No assignment to bit2
@W: CG133 :"C:\Actelprj\PWM\hdl\PWM_contr.v":17:12:17:16|No assignment to data0
@W: CG133 :"C:\Actelprj\PWM\hdl\PWM_contr.v":17:18:17:22|No assignment to data1
@W: CG360 :"C:\Actelprj\PWM\hdl\PWM_contr.v":24:16:24:22|No assignment to wire key_buf

@N: CG364 :"C:\Actelprj\PWM\hdl\TOP.v":2:7:2:9|Synthesizing module top

@W: CS148 :"C:\Actelprj\PWM\hdl\TOP.v":24:8:24:9|Undriven input OADIVRST, tying to 0
@N: CL201 :"C:\Actelprj\PWM\hdl\PWM_contr.v":52:0:52:5|Trying to extract state machine for register status
Extracted state machine for register status
State machine has 4 reachable states with original encodings of:
   00001
   00010
   00100
   01000