📄 top.srr
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u0.un1_counter_0.I_213 OA1A Y Out 0.662 4.603 -
N_41_0 Net - - 0.313 - 1
u0.un1_counter_0.I_214 OA1 A In - 4.916 -
u0.un1_counter_0.I_214 OA1 Y Out 0.720 5.636 -
DWACT_CMPLE_PO2_DWACT_COMP0_E_3[0] Net - - 0.313 - 1
u0.un1_counter_0.I_238 AO1 C In - 5.949 -
u0.un1_counter_0.I_238 AO1 Y Out 0.475 6.425 -
DWACT_CMPLE_PO2_DWACT_COMP0_E_2[2] Net - - 0.313 - 1
u0.un1_counter_0.I_243 AO1 B In - 6.738 -
u0.un1_counter_0.I_243 AO1 Y Out 0.428 7.166 -
DWACT_COMP0_E[2] Net - - 0.736 - 3
u0.un1_counter_0.I_248_1 AO1 B In - 7.901 -
u0.un1_counter_0.I_248_1 AO1 Y Out 0.428 8.329 -
un1_counter_1 Net - - 2.083 - 11
u0.counter_5[10] NOR2B B In - 10.412 -
u0.counter_5[10] NOR2B Y Out 0.460 10.871 -
counter_5[10] Net - - 0.313 - 1
u0.counter[10] DFN1C1 D In - 11.184 -
===================================================================================================
Total path delay (propagation time + setup) of 11.594 is 4.914(42.4%) logic and 6.680(57.6%) route.
Path information for path number 3:
Requested Period: 10.000
- Setup time: 0.410
= Required time: 9.590
- Propagation time: 11.184
= Slack (non-critical) : -1.594
Number of logic level(s): 8
Starting point: u0.counter[6] / Q
Ending point: u0.counter[22] / D
The start point is clocked by top|u1.GLA_inferred_clock [rising] on pin CLK
The end point is clocked by top|u1.GLA_inferred_clock [rising] on pin CLK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
---------------------------------------------------------------------------------------------------
u0.counter[6] DFN1C1 Q Out 0.382 0.382 -
counter[6] Net - - 1.983 - 10
u0.un1_counter_0.I_204 OR2A B In - 2.365 -
u0.un1_counter_0.I_204 OR2A Y Out 0.474 2.839 -
N_32_0 Net - - 0.313 - 1
u0.un1_counter_0.I_210 AO1C C In - 3.152 -
u0.un1_counter_0.I_210 AO1C Y Out 0.475 3.628 -
N_38_0 Net - - 0.313 - 1
u0.un1_counter_0.I_213 OA1A B In - 3.941 -
u0.un1_counter_0.I_213 OA1A Y Out 0.662 4.603 -
N_41_0 Net - - 0.313 - 1
u0.un1_counter_0.I_214 OA1 A In - 4.916 -
u0.un1_counter_0.I_214 OA1 Y Out 0.720 5.636 -
DWACT_CMPLE_PO2_DWACT_COMP0_E_3[0] Net - - 0.313 - 1
u0.un1_counter_0.I_238 AO1 C In - 5.949 -
u0.un1_counter_0.I_238 AO1 Y Out 0.475 6.425 -
DWACT_CMPLE_PO2_DWACT_COMP0_E_2[2] Net - - 0.313 - 1
u0.un1_counter_0.I_243 AO1 B In - 6.738 -
u0.un1_counter_0.I_243 AO1 Y Out 0.428 7.166 -
DWACT_COMP0_E[2] Net - - 0.736 - 3
u0.un1_counter_0.I_248_0 AO1 B In - 7.901 -
u0.un1_counter_0.I_248_0 AO1 Y Out 0.428 8.329 -
un1_counter_0 Net - - 2.083 - 11
u0.counter_5[22] NOR2B B In - 10.412 -
u0.counter_5[22] NOR2B Y Out 0.460 10.871 -
counter_5[22] Net - - 0.313 - 1
u0.counter[22] DFN1C1 D In - 11.184 -
===================================================================================================
Total path delay (propagation time + setup) of 11.594 is 4.914(42.4%) logic and 6.680(57.6%) route.
Path information for path number 4:
Requested Period: 10.000
- Setup time: 0.410
= Required time: 9.590
- Propagation time: 11.184
= Slack (non-critical) : -1.594
Number of logic level(s): 8
Starting point: u0.counter[6] / Q
Ending point: u0.counter[23] / D
The start point is clocked by top|u1.GLA_inferred_clock [rising] on pin CLK
The end point is clocked by top|u1.GLA_inferred_clock [rising] on pin CLK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
---------------------------------------------------------------------------------------------------
u0.counter[6] DFN1C1 Q Out 0.382 0.382 -
counter[6] Net - - 1.983 - 10
u0.un1_counter_0.I_204 OR2A B In - 2.365 -
u0.un1_counter_0.I_204 OR2A Y Out 0.474 2.839 -
N_32_0 Net - - 0.313 - 1
u0.un1_counter_0.I_210 AO1C C In - 3.152 -
u0.un1_counter_0.I_210 AO1C Y Out 0.475 3.628 -
N_38_0 Net - - 0.313 - 1
u0.un1_counter_0.I_213 OA1A B In - 3.941 -
u0.un1_counter_0.I_213 OA1A Y Out 0.662 4.603 -
N_41_0 Net - - 0.313 - 1
u0.un1_counter_0.I_214 OA1 A In - 4.916 -
u0.un1_counter_0.I_214 OA1 Y Out 0.720 5.636 -
DWACT_CMPLE_PO2_DWACT_COMP0_E_3[0] Net - - 0.313 - 1
u0.un1_counter_0.I_238 AO1 C In - 5.949 -
u0.un1_counter_0.I_238 AO1 Y Out 0.475 6.425 -
DWACT_CMPLE_PO2_DWACT_COMP0_E_2[2] Net - - 0.313 - 1
u0.un1_counter_0.I_243 AO1 B In - 6.738 -
u0.un1_counter_0.I_243 AO1 Y Out 0.428 7.166 -
DWACT_COMP0_E[2] Net - - 0.736 - 3
u0.un1_counter_0.I_248_0 AO1 B In - 7.901 -
u0.un1_counter_0.I_248_0 AO1 Y Out 0.428 8.329 -
un1_counter_0 Net - - 2.083 - 11
u0.counter_5[23] NOR2B B In - 10.412 -
u0.counter_5[23] NOR2B Y Out 0.460 10.871 -
counter_5[23] Net - - 0.313 - 1
u0.counter[23] DFN1C1 D In - 11.184 -
===================================================================================================
Total path delay (propagation time + setup) of 11.594 is 4.914(42.4%) logic and 6.680(57.6%) route.
Path information for path number 5:
Requested Period: 10.000
- Setup time: 0.410
= Required time: 9.590
- Propagation time: 11.184
= Slack (non-critical) : -1.594
Number of logic level(s): 8
Starting point: u0.counter[6] / Q
Ending point: u0.counter[24] / D
The start point is clocked by top|u1.GLA_inferred_clock [rising] on pin CLK
The end point is clocked by top|u1.GLA_inferred_clock [rising] on pin CLK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
---------------------------------------------------------------------------------------------------
u0.counter[6] DFN1C1 Q Out 0.382 0.382 -
counter[6] Net - - 1.983 - 10
u0.un1_counter_0.I_204 OR2A B In - 2.365 -
u0.un1_counter_0.I_204 OR2A Y Out 0.474 2.839 -
N_32_0 Net - - 0.313 - 1
u0.un1_counter_0.I_210 AO1C C In - 3.152 -
u0.un1_counter_0.I_210 AO1C Y Out 0.475 3.628 -
N_38_0 Net - - 0.313 - 1
u0.un1_counter_0.I_213 OA1A B In - 3.941 -
u0.un1_counter_0.I_213 OA1A Y Out 0.662 4.603 -
N_41_0 Net - - 0.313 - 1
u0.un1_counter_0.I_214 OA1 A In - 4.916 -
u0.un1_counter_0.I_214 OA1 Y Out 0.720 5.636 -
DWACT_CMPLE_PO2_DWACT_COMP0_E_3[0] Net - - 0.313 - 1
u0.un1_counter_0.I_238 AO1 C In - 5.949 -
u0.un1_counter_0.I_238 AO1 Y Out 0.475 6.425 -
DWACT_CMPLE_PO2_DWACT_COMP0_E_2[2] Net - - 0.313 - 1
u0.un1_counter_0.I_243 AO1 B In - 6.738 -
u0.un1_counter_0.I_243 AO1 Y Out 0.428 7.166 -
DWACT_COMP0_E[2] Net - - 0.736 - 3
u0.un1_counter_0.I_248_0 AO1 B In - 7.901 -
u0.un1_counter_0.I_248_0 AO1 Y Out 0.428 8.329 -
un1_counter_0 Net - - 2.083 - 11
u0.counter_5[24] NOR2B B In - 10.412 -
u0.counter_5[24] NOR2B Y Out 0.460 10.871 -
counter_5[24] Net - - 0.313 - 1
u0.counter[24] DFN1C1 D In - 11.184 -
===================================================================================================
Total path delay (propagation time + setup) of 11.594 is 4.914(42.4%) logic and 6.680(57.6%) route.
##### END OF TIMING REPORT #####]
--------------------------------------------------------------------------------
Report for cell top.verilog
Core Cell usage:
cell count area count*area
XNOR2 78 1.0 78.0
AND3 75 1.0 75.0
DFN1E0C1 65 1.0 65.0
OR2A 53 1.0 53.0
DFN1C1 51 1.0 51.0
NOR2B 46 1.0 46.0
XOR2 44 1.0 44.0
AO1C 30 1.0 30.0
AND2 29 1.0 29.0
NOR2A 25 1.0 25.0
OA1A 22 1.0 22.0
AO1 13 1.0 13.0
OA1 11 1.0 11.0
AOI1A 10 1.0 10.0
DFN1E1C1 9 1.0 9.0
NOR3A 8 1.0 8.0
AND2A 6 1.0 6.0
OR3B 6 1.0 6.0
OR2 5 1.0 5.0
GND 4 0.0 0.0
OR3A 4 1.0 4.0
VCC 4 0.0 0.0
NOR2 4 1.0 4.0
OR3C 2 1.0 2.0
BUFF 2 1.0 2.0
AO1D 2 1.0 2.0
NOR3C 2 1.0 2.0
NOR3B 2 1.0 2.0
CLKINT 1 0.0 0.0
OR3 1 1.0 1.0
NOR3 1 1.0 1.0
OAI1 1 1.0 1.0
INV 1 1.0 1.0
PLLINT 1 0.0 0.0
OA1B 1 1.0 1.0
OR2B 1 1.0 1.0
AOI5 1 1.0 1.0
PLL 1 0.0 0.0
AOI1B 1 1.0 1.0
AOI1 1 1.0 1.0
----- ----------
TOTAL 624 613.0
IO Cell usage:
cell count
INBUF 2
OUTBUF 1
-----
TOTAL 3
Mapper successful!
Process took 0h:00m:13s realtime, 0h:00m:03s cputime
# Thu Sep 27 09:13:38 2007
###########################################################]
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