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u2.un1_status_4_i_0 NOR2B Y Out 0.384 5.726 -
un1_status_4_i_0 Net - - 0.527 - 2
u2.un1_cou_1.I_1 AND2 B In - 6.253 -
u2.un1_cou_1.I_1 AND2 Y Out 0.460 6.712 -
DWACT_ADD_CI_0_TMP_0[0] Net - - 0.527 - 2
u2.un1_cou_1.I_26 NOR2B A In - 7.239 -
u2.un1_cou_1.I_26 NOR2B Y Out 0.384 7.623 -
DWACT_ADD_CI_0_g_array_1[0] Net - - 0.736 - 3
u2.un1_cou_1.I_25 NOR2B A In - 8.358 -
u2.un1_cou_1.I_25 NOR2B Y Out 0.384 8.742 -
DWACT_ADD_CI_0_g_array_12[0] Net - - 0.313 - 1
u2.un1_cou_1.I_21 XOR2 B In - 9.055 -
u2.un1_cou_1.I_21 XOR2 Y Out 0.681 9.736 -
I_21 Net - - 0.313 - 1
u2.cou_16_0_a3[3] NOR3A A In - 10.049 -
u2.cou_16_0_a3[3] NOR3A Y Out 0.483 10.532 -
cou_16[3] Net - - 0.313 - 1
u2.cou[3] DFN1C1 D In - 10.845 -
=============================================================================================
Total path delay (propagation time + setup) of 11.155 is 5.195(46.6%) logic and 5.960(53.4%) route.
====================================
Detailed Report for Clock: top|CLK48M
====================================
Starting Points with Worst Slack
********************************
Starting Arrival
Instance Reference Type Pin Net Time Slack
Clock
--------------------------------------------------------------------------------
u2.count[1] top|CLK48M DFN1C1 Q count[1] 0.476 5.079
u2.count[0] top|CLK48M DFN1C1 Q count[0] 0.476 5.159
u2.count[2] top|CLK48M DFN1C1 Q count[2] 0.476 5.277
u2.count[3] top|CLK48M DFN1C1 Q count[3] 0.382 5.559
u2.count[4] top|CLK48M DFN1C1 Q count[4] 0.382 5.783
================================================================================
Ending Points with Worst Slack
******************************
Starting Required
Instance Reference Type Pin Net Time Slack
Clock
-------------------------------------------------------------------------------------
u2.count[4] top|CLK48M DFN1C1 D count_5[4] 9.590 5.079
u2.count[0] top|CLK48M DFN1C1 D count_5[0] 9.590 5.379
u2.count[3] top|CLK48M DFN1C1 D count_5[3] 9.590 5.379
u2.clk1m top|CLK48M DFN1E0C1 E clk1m6 9.650 6.211
u2.count[2] top|CLK48M DFN1C1 D I_9_0 9.590 6.557
u2.count[1] top|CLK48M DFN1C1 D I_5_0 9.690 7.062
=====================================================================================
Worst Path Information
***********************
Path information for path number 1:
Requested Period: 10.000
- Setup time: 0.410
= Required time: 9.590
- Propagation time: 4.511
= Slack (non-critical) : 5.079
Number of logic level(s): 4
Starting point: u2.count[1] / Q
Ending point: u2.count[4] / D
The start point is clocked by top|CLK48M [rising] on pin CLK
The end point is clocked by top|CLK48M [rising] on pin CLK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
------------------------------------------------------------------------------------
u2.count[1] DFN1C1 Q Out 0.476 0.476 -
count[1] Net - - 1.158 - 5
u2.un6_count_1.I_16 AND3 B In - 1.635 -
u2.un6_count_1.I_16 AND3 Y Out 0.469 2.103 -
DWACT_FINC_E[0] Net - - 0.313 - 1
u2.un6_count_1.I_19 NOR2B B In - 2.416 -
u2.un6_count_1.I_19 NOR2B Y Out 0.460 2.876 -
N_4 Net - - 0.313 - 1
u2.un6_count_1.I_20 XOR2 A In - 3.189 -
u2.un6_count_1.I_20 XOR2 Y Out 0.313 3.502 -
I_20_1 Net - - 0.313 - 1
u2.count_5[4] NOR2B A In - 3.815 -
u2.count_5[4] NOR2B Y Out 0.384 4.198 -
count_5[4] Net - - 0.313 - 1
u2.count[4] DFN1C1 D In - 4.511 -
====================================================================================
Total path delay (propagation time + setup) of 4.921 is 2.511(51.0%) logic and 2.410(49.0%) route.
====================================
Detailed Report for Clock: top|u1.GLA_inferred_clock
====================================
Starting Points with Worst Slack
********************************
Starting Arrival
Instance Reference Type Pin Net Time Slack
Clock
------------------------------------------------------------------------------------------------------
u0.counter[6] top|u1.GLA_inferred_clock DFN1C1 Q counter[6] 0.382 -1.594
u0.counter[1] top|u1.GLA_inferred_clock DFN1C1 Q counter[1] 0.382 -1.378
u0.counter[11] top|u1.GLA_inferred_clock DFN1C1 Q counter[11] 0.382 -1.261
u0.counter[20] top|u1.GLA_inferred_clock DFN1C1 Q counter[20] 0.382 -1.261
u0.counter[0] top|u1.GLA_inferred_clock DFN1C1 Q counter[0] 0.382 -1.058
u0.counter[12] top|u1.GLA_inferred_clock DFN1C1 Q counter[12] 0.382 -1.008
u0.counter[21] top|u1.GLA_inferred_clock DFN1C1 Q counter[21] 0.382 -1.008
u0.counter[28] top|u1.GLA_inferred_clock DFN1C1 Q counter[28] 0.382 -1.000
u0.counter[5] top|u1.GLA_inferred_clock DFN1C1 Q counter[5] 0.382 -0.942
u0.counter[10] top|u1.GLA_inferred_clock DFN1C1 Q counter[10] 0.382 -0.942
======================================================================================================
Ending Points with Worst Slack
******************************
Starting Required
Instance Reference Type Pin Net Time Slack
Clock
---------------------------------------------------------------------------------------------------------
u0.counter[10] top|u1.GLA_inferred_clock DFN1C1 D counter_5[10] 9.590 -1.594
u0.counter[11] top|u1.GLA_inferred_clock DFN1C1 D counter_5[11] 9.590 -1.594
u0.counter[12] top|u1.GLA_inferred_clock DFN1C1 D counter_5[12] 9.590 -1.594
u0.counter[13] top|u1.GLA_inferred_clock DFN1C1 D counter_5[13] 9.590 -1.594
u0.counter[14] top|u1.GLA_inferred_clock DFN1C1 D counter_5[14] 9.590 -1.594
u0.counter[15] top|u1.GLA_inferred_clock DFN1C1 D counter_5[15] 9.590 -1.594
u0.counter[16] top|u1.GLA_inferred_clock DFN1C1 D counter_5[16] 9.590 -1.594
u0.counter[17] top|u1.GLA_inferred_clock DFN1C1 D counter_5[17] 9.590 -1.594
u0.counter[18] top|u1.GLA_inferred_clock DFN1C1 D counter_5[18] 9.590 -1.594
u0.counter[19] top|u1.GLA_inferred_clock DFN1C1 D counter_5[19] 9.590 -1.594
=========================================================================================================
Worst Path Information
***********************
Path information for path number 1:
Requested Period: 10.000
- Setup time: 0.410
= Required time: 9.590
- Propagation time: 11.184
= Slack (non-critical) : -1.594
Number of logic level(s): 8
Starting point: u0.counter[6] / Q
Ending point: u0.counter[21] / D
The start point is clocked by top|u1.GLA_inferred_clock [rising] on pin CLK
The end point is clocked by top|u1.GLA_inferred_clock [rising] on pin CLK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
---------------------------------------------------------------------------------------------------
u0.counter[6] DFN1C1 Q Out 0.382 0.382 -
counter[6] Net - - 1.983 - 10
u0.un1_counter_0.I_204 OR2A B In - 2.365 -
u0.un1_counter_0.I_204 OR2A Y Out 0.474 2.839 -
N_32_0 Net - - 0.313 - 1
u0.un1_counter_0.I_210 AO1C C In - 3.152 -
u0.un1_counter_0.I_210 AO1C Y Out 0.475 3.628 -
N_38_0 Net - - 0.313 - 1
u0.un1_counter_0.I_213 OA1A B In - 3.941 -
u0.un1_counter_0.I_213 OA1A Y Out 0.662 4.603 -
N_41_0 Net - - 0.313 - 1
u0.un1_counter_0.I_214 OA1 A In - 4.916 -
u0.un1_counter_0.I_214 OA1 Y Out 0.720 5.636 -
DWACT_CMPLE_PO2_DWACT_COMP0_E_3[0] Net - - 0.313 - 1
u0.un1_counter_0.I_238 AO1 C In - 5.949 -
u0.un1_counter_0.I_238 AO1 Y Out 0.475 6.425 -
DWACT_CMPLE_PO2_DWACT_COMP0_E_2[2] Net - - 0.313 - 1
u0.un1_counter_0.I_243 AO1 B In - 6.738 -
u0.un1_counter_0.I_243 AO1 Y Out 0.428 7.166 -
DWACT_COMP0_E[2] Net - - 0.736 - 3
u0.un1_counter_0.I_248_0 AO1 B In - 7.901 -
u0.un1_counter_0.I_248_0 AO1 Y Out 0.428 8.329 -
un1_counter_0 Net - - 2.083 - 11
u0.counter_5[21] NOR2B B In - 10.412 -
u0.counter_5[21] NOR2B Y Out 0.460 10.871 -
counter_5[21] Net - - 0.313 - 1
u0.counter[21] DFN1C1 D In - 11.184 -
===================================================================================================
Total path delay (propagation time + setup) of 11.594 is 4.914(42.4%) logic and 6.680(57.6%) route.
Path information for path number 2:
Requested Period: 10.000
- Setup time: 0.410
= Required time: 9.590
- Propagation time: 11.184
= Slack (non-critical) : -1.594
Number of logic level(s): 8
Starting point: u0.counter[6] / Q
Ending point: u0.counter[10] / D
The start point is clocked by top|u1.GLA_inferred_clock [rising] on pin CLK
The end point is clocked by top|u1.GLA_inferred_clock [rising] on pin CLK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
---------------------------------------------------------------------------------------------------
u0.counter[6] DFN1C1 Q Out 0.382 0.382 -
counter[6] Net - - 1.983 - 10
u0.un1_counter_0.I_204 OR2A B In - 2.365 -
u0.un1_counter_0.I_204 OR2A Y Out 0.474 2.839 -
N_32_0 Net - - 0.313 - 1
u0.un1_counter_0.I_210 AO1C C In - 3.152 -
u0.un1_counter_0.I_210 AO1C Y Out 0.475 3.628 -
N_38_0 Net - - 0.313 - 1
u0.un1_counter_0.I_213 OA1A B In - 3.941 -
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