📄 top.srr
字号:
Ending Points with Worst Slack
******************************
Starting Required
Instance Reference Type Pin Net Time Slack
Clock
------------------------------------------------------------------------------------------------------
u2.addr[2] control|clk1m_inferred_clock DFN1C1 D addr_8[2] 9.690 -1.890
u2.addr[1] control|clk1m_inferred_clock DFN1C1 D addr_8[1] 9.690 -1.220
u2.addr_0[1] control|clk1m_inferred_clock DFN1C1 D addr_8[1] 9.690 -1.220
u2.cou[3] control|clk1m_inferred_clock DFN1C1 D cou_16[3] 9.690 -1.155
u2.cou[4] control|clk1m_inferred_clock DFN1C1 D cou_16[4] 9.690 -1.155
u2.cou[2] control|clk1m_inferred_clock DFN1C1 D cou_16[2] 9.690 -0.458
u2.addr[0] control|clk1m_inferred_clock DFN1C1 D addr_8[0] 9.690 -0.233
u2.addr_0[0] control|clk1m_inferred_clock DFN1C1 D addr_8[0] 9.690 -0.233
u2.cou[1] control|clk1m_inferred_clock DFN1C1 D cou_16[1] 9.690 0.661
u2.cou[0] control|clk1m_inferred_clock DFN1C1 D cou_16[0] 9.590 0.822
======================================================================================================
Worst Path Information
***********************
Path information for path number 1:
Requested Period: 10.000
- Setup time: 0.310
= Required time: 9.690
- Propagation time: 11.579
= Slack (critical) : -1.890
Number of logic level(s): 7
Starting point: u2.status[0] / Q
Ending point: u2.addr[2] / D
The start point is clocked by control|clk1m_inferred_clock [rising] on pin CLK
The end point is clocked by control|clk1m_inferred_clock [rising] on pin CLK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-----------------------------------------------------------------------------------------
u2.status[0] DFN1C1 Q Out 0.476 0.476 -
status[0] Net - - 1.983 - 10
u2.un1_status_i_x2_i_x2 XOR2 B In - 2.460 -
u2.un1_status_i_x2_i_x2 XOR2 Y Out 0.681 3.140 -
N_42_i_0 Net - - 1.814 - 9
u2.un1_status_6_0_0_a3_0 OR3C C In - 4.955 -
u2.un1_status_6_0_0_a3_0 OR3C Y Out 0.484 5.439 -
N_72 Net - - 0.527 - 2
u2.un1_status_6_0_0 OAI1 C In - 5.966 -
u2.un1_status_6_0_0 OAI1 Y Out 0.475 6.441 -
un1_status_6_0_0 Net - - 1.486 - 7
u2.un1_addr_1.I_1 AND2 B In - 7.927 -
u2.un1_addr_1.I_1 AND2 Y Out 0.460 8.387 -
DWACT_ADD_CI_0_TMP[0] Net - - 0.527 - 2
u2.un1_addr_1.I_15 NOR2B A In - 8.914 -
u2.un1_addr_1.I_15 NOR2B Y Out 0.384 9.297 -
I_15 Net - - 0.313 - 1
u2.un1_addr_1.I_14 XOR2 B In - 9.610 -
u2.un1_addr_1.I_14 XOR2 Y Out 0.681 10.291 -
I_14 Net - - 0.313 - 1
u2.addr_8_r[2] OA1 B In - 10.604 -
u2.addr_8_r[2] OA1 Y Out 0.662 11.266 -
addr_8[2] Net - - 0.313 - 1
u2.addr[2] DFN1C1 D In - 11.579 -
=========================================================================================
Total path delay (propagation time + setup) of 11.890 is 4.613(38.8%) logic and 7.277(61.2%) route.
Path information for path number 2:
Requested Period: 10.000
- Setup time: 0.310
= Required time: 9.690
- Propagation time: 11.091
= Slack (non-critical) : -1.401
Number of logic level(s): 7
Starting point: u2.status[1] / Q
Ending point: u2.addr[2] / D
The start point is clocked by control|clk1m_inferred_clock [rising] on pin CLK
The end point is clocked by control|clk1m_inferred_clock [rising] on pin CLK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-----------------------------------------------------------------------------------------
u2.status[1] DFN1C1 Q Out 0.476 0.476 -
status[1] Net - - 1.814 - 9
u2.un1_status_i_x2_i_x2 XOR2 A In - 2.291 -
u2.un1_status_i_x2_i_x2 XOR2 Y Out 0.361 2.652 -
N_42_i_0 Net - - 1.814 - 9
u2.un1_status_6_0_0_a3_0 OR3C C In - 4.466 -
u2.un1_status_6_0_0_a3_0 OR3C Y Out 0.484 4.950 -
N_72 Net - - 0.527 - 2
u2.un1_status_6_0_0 OAI1 C In - 5.477 -
u2.un1_status_6_0_0 OAI1 Y Out 0.475 5.953 -
un1_status_6_0_0 Net - - 1.486 - 7
u2.un1_addr_1.I_1 AND2 B In - 7.439 -
u2.un1_addr_1.I_1 AND2 Y Out 0.460 7.898 -
DWACT_ADD_CI_0_TMP[0] Net - - 0.527 - 2
u2.un1_addr_1.I_15 NOR2B A In - 8.425 -
u2.un1_addr_1.I_15 NOR2B Y Out 0.384 8.809 -
I_15 Net - - 0.313 - 1
u2.un1_addr_1.I_14 XOR2 B In - 9.122 -
u2.un1_addr_1.I_14 XOR2 Y Out 0.681 9.803 -
I_14 Net - - 0.313 - 1
u2.addr_8_r[2] OA1 B In - 10.116 -
u2.addr_8_r[2] OA1 Y Out 0.662 10.778 -
addr_8[2] Net - - 0.313 - 1
u2.addr[2] DFN1C1 D In - 11.091 -
=========================================================================================
Total path delay (propagation time + setup) of 11.401 is 4.293(37.7%) logic and 7.108(62.3%) route.
Path information for path number 3:
Requested Period: 10.000
- Setup time: 0.310
= Required time: 9.690
- Propagation time: 10.910
= Slack (non-critical) : -1.220
Number of logic level(s): 6
Starting point: u2.status[0] / Q
Ending point: u2.addr[1] / D
The start point is clocked by control|clk1m_inferred_clock [rising] on pin CLK
The end point is clocked by control|clk1m_inferred_clock [rising] on pin CLK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-----------------------------------------------------------------------------------------
u2.status[0] DFN1C1 Q Out 0.476 0.476 -
status[0] Net - - 1.983 - 10
u2.un1_status_i_x2_i_x2 XOR2 B In - 2.460 -
u2.un1_status_i_x2_i_x2 XOR2 Y Out 0.681 3.140 -
N_42_i_0 Net - - 1.814 - 9
u2.un1_status_6_0_0_a3_0 OR3C C In - 4.955 -
u2.un1_status_6_0_0_a3_0 OR3C Y Out 0.484 5.439 -
N_72 Net - - 0.527 - 2
u2.un1_status_6_0_0 OAI1 C In - 5.966 -
u2.un1_status_6_0_0 OAI1 Y Out 0.475 6.441 -
un1_status_6_0_0 Net - - 1.486 - 7
u2.un1_addr_1.I_1 AND2 B In - 7.927 -
u2.un1_addr_1.I_1 AND2 Y Out 0.460 8.387 -
DWACT_ADD_CI_0_TMP[0] Net - - 0.527 - 2
u2.un1_addr_1.I_13 XOR2 B In - 8.914 -
u2.un1_addr_1.I_13 XOR2 Y Out 0.681 9.594 -
I_13_0 Net - - 0.313 - 1
u2.addr_8_0[1] AO1D C In - 9.907 -
u2.addr_8_0[1] AO1D Y Out 0.475 10.383 -
addr_8[1] Net - - 0.527 - 2
u2.addr[1] DFN1C1 D In - 10.910 -
=========================================================================================
Total path delay (propagation time + setup) of 11.220 is 4.042(36.0%) logic and 7.177(64.0%) route.
Path information for path number 4:
Requested Period: 10.000
- Setup time: 0.310
= Required time: 9.690
- Propagation time: 10.910
= Slack (non-critical) : -1.220
Number of logic level(s): 6
Starting point: u2.status[0] / Q
Ending point: u2.addr_0[1] / D
The start point is clocked by control|clk1m_inferred_clock [rising] on pin CLK
The end point is clocked by control|clk1m_inferred_clock [rising] on pin CLK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-----------------------------------------------------------------------------------------
u2.status[0] DFN1C1 Q Out 0.476 0.476 -
status[0] Net - - 1.983 - 10
u2.un1_status_i_x2_i_x2 XOR2 B In - 2.460 -
u2.un1_status_i_x2_i_x2 XOR2 Y Out 0.681 3.140 -
N_42_i_0 Net - - 1.814 - 9
u2.un1_status_6_0_0_a3_0 OR3C C In - 4.955 -
u2.un1_status_6_0_0_a3_0 OR3C Y Out 0.484 5.439 -
N_72 Net - - 0.527 - 2
u2.un1_status_6_0_0 OAI1 C In - 5.966 -
u2.un1_status_6_0_0 OAI1 Y Out 0.475 6.441 -
un1_status_6_0_0 Net - - 1.486 - 7
u2.un1_addr_1.I_1 AND2 B In - 7.927 -
u2.un1_addr_1.I_1 AND2 Y Out 0.460 8.387 -
DWACT_ADD_CI_0_TMP[0] Net - - 0.527 - 2
u2.un1_addr_1.I_13 XOR2 B In - 8.914 -
u2.un1_addr_1.I_13 XOR2 Y Out 0.681 9.594 -
I_13_0 Net - - 0.313 - 1
u2.addr_8_0[1] AO1D C In - 9.907 -
u2.addr_8_0[1] AO1D Y Out 0.475 10.383 -
addr_8[1] Net - - 0.527 - 2
u2.addr_0[1] DFN1C1 D In - 10.910 -
=========================================================================================
Total path delay (propagation time + setup) of 11.220 is 4.042(36.0%) logic and 7.177(64.0%) route.
Path information for path number 5:
Requested Period: 10.000
- Setup time: 0.310
= Required time: 9.690
- Propagation time: 10.845
= Slack (non-critical) : -1.155
Number of logic level(s): 9
Starting point: u2.addr[2] / Q
Ending point: u2.cou[3] / D
The start point is clocked by control|clk1m_inferred_clock [rising] on pin CLK
The end point is clocked by control|clk1m_inferred_clock [rising] on pin CLK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
---------------------------------------------------------------------------------------------
u2.addr[2] DFN1C1 Q Out 0.476 0.476 -
addr[2] Net - - 1.650 - 8
u2.N_109_m_i_a2_0 OR3C C In - 2.127 -
u2.N_109_m_i_a2_0 OR3C Y Out 0.484 2.611 -
N_92 Net - - 0.527 - 2
u2.status_ns_1_iv_0_a3_0[0] OA1A A In - 3.138 -
u2.status_ns_1_iv_0_a3_0[0] OA1A Y Out 0.677 3.815 -
N_74 Net - - 0.527 - 2
u2.un1_status_4_i_0_o3 NOR2 B In - 4.342 -
u2.un1_status_4_i_0_o3 NOR2 Y Out 0.474 4.816 -
N_80 Net - - 0.527 - 2
u2.un1_status_4_i_0 NOR2B A In - 5.342 -
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -