top.srr

Core_PWM,verilog语言编写

#Build: Synplify Pro 8.6.2H, Build 017R, Dec  7 2006
#install: D:\Libero\Synplify\Synplify_862H
#OS: Windows XP 5.1
#Hostname: SHOUJINQIAO

#Thu Sep 27 09:13:21 2007

$ Start of Compile
#Thu Sep 27 09:13:21 2007

Synplicity Verilog Compiler, version 3.7, Build 090R, built Nov 17 2006
Copyright (C) 1994-2006, Synplicity Inc.  All Rights Reserved

@I::"D:\Libero\Synplify\Synplify_862H\lib\proasic\fusion.v"
@I::"C:\Actelprj\PWM\hdl\PWM.v"
@I::"C:\Actelprj\PWM\hdl\PWM_contr.v"
@I::"C:\Actelprj\PWM\smartgen\PLL_1\PLL_1.v"
@I::"C:\Actelprj\PWM\hdl\TOP.v"
Verilog syntax check successful!
File C:\Actelprj\PWM\smartgen\PLL_1\PLL_1.v changed - recompiling
File C:\Actelprj\PWM\hdl\PWM_contr.v changed - recompiling
Selecting top level module top
@N: CG364 :"C:\Actelprj\PWM\hdl\PWM.v":2:7:2:9|Synthesizing module PWM

@N: CG364 :"D:\Libero\Synplify\Synplify_862H\lib\proasic\fusion.v":2043:7:2043:9|Synthesizing module VCC

@N: CG364 :"D:\Libero\Synplify\Synplify_862H\lib\proasic\fusion.v":1224:7:1224:9|Synthesizing module GND

@N: CG364 :"D:\Libero\Synplify\Synplify_862H\lib\proasic\fusion.v":2974:7:2974:9|Synthesizing module PLL

@N: CG364 :"D:\Libero\Synplify\Synplify_862H\lib\proasic\fusion.v":260:7:260:12|Synthesizing module PLLINT

@N: CG364 :"C:\Actelprj\PWM\smartgen\PLL_1\PLL_1.v":5:7:5:11|Synthesizing module PLL_1

@N: CG364 :"C:\Actelprj\PWM\hdl\PWM_contr.v":2:7:2:13|Synthesizing module control

@W: CG133 :"C:\Actelprj\PWM\hdl\PWM_contr.v":15:12:15:15|No assignment to bit0
@W: CG133 :"C:\Actelprj\PWM\hdl\PWM_contr.v":15:17:15:20|No assignment to bit1
@W: CG133 :"C:\Actelprj\PWM\hdl\PWM_contr.v":15:22:15:25|No assignment to bit2
@W: CG133 :"C:\Actelprj\PWM\hdl\PWM_contr.v":17:12:17:16|No assignment to data0
@W: CG133 :"C:\Actelprj\PWM\hdl\PWM_contr.v":17:18:17:22|No assignment to data1
@W: CG360 :"C:\Actelprj\PWM\hdl\PWM_contr.v":24:16:24:22|No assignment to wire key_buf

@N: CG364 :"C:\Actelprj\PWM\hdl\TOP.v":2:7:2:9|Synthesizing module top

@W: CS148 :"C:\Actelprj\PWM\hdl\TOP.v":24:8:24:9|Undriven input OADIVRST, tying to 0
@N: CL201 :"C:\Actelprj\PWM\hdl\PWM_contr.v":52:0:52:5|Trying to extract state machine for register status
Extracted state machine for register status
State machine has 4 reachable states with original encodings of:
   00001
   00010
   00100
   01000
@END
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Thu Sep 27 09:13:22 2007

###########################################################]
Synplicity Proasic Technology Mapper, Version 9.0.0, Build 368R, Built Nov 27 2006 12:29:38
Copyright (C) 1994-2006, Synplicity Inc.  All Rights Reserved
Product Version Version 8.6.2H
Reading constraint file: C:\Actelprj\PWM\constraint\top_sdc.sdc
@N: MF249 |Running in 32-bit mode.
@N: MF258 |Gated clock conversion disabled 
Adding property syn_noclockbuf, value 1, to port rst
@W: BN153 |View "prim", Cell "NGMUX", Port "CLK0": remove clock marking
@W: BN153 |View "prim", Cell "NGMUX", Port "CLK1": remove clock marking
@W: BN154 |View "prim" of Cell "NGMUX": 4 sequential timing arcs are removed


Automatic dissolve at startup in view:work.top(verilog) of u1(PLL_1)
RTL optimization done.

Finished RTL optimizations (Time elapsed 0h:00m:00s; Memory used current: 43MB peak: 45MB)
@N: MF179 :"c:\actelprj\pwm\hdl\pwm.v":25:6:25:31|Found 32 bit by 32 bit '<' comparator, 'un1_counter'
@N: MF179 :"c:\actelprj\pwm\hdl\pwm.v":38:6:38:29|Found 32 bit by 32 bit '<' comparator, 'un1_duty_cycle_r'
@N: MF238 :"c:\actelprj\pwm\hdl\pwm.v":28:14:28:25|Found 32 bit incrementor, 'un8_counter[31:0]'
Encoding state machine work.control(verilog)-status[3:0]
original code -> new code
   00001 -> 00
   00010 -> 01
   00100 -> 10
   01000 -> 11
@N: MF238 :"c:\actelprj\pwm\hdl\pwm_contr.v":48:17:48:26|Found 5 bit incrementor, 'un6_count_1[4:0]'
Automatic dissolve during optimization of view:work.control(verilog) of un10_data(PM_RSH__32_32_6_AFS600-1)

Finished factoring (Time elapsed 0h:00m:01s; Memory used current: 45MB peak: 45MB)
@W: BN116 :"c:\actelprj\pwm\hdl\pwm.v":95:0:95:5|Removing sequential instance u0.wb_dat_o[7] of view:PrimLib.dff(prim) because there are no references to its outputs 
@W: BN116 :"c:\actelprj\pwm\hdl\pwm.v":95:0:95:5|Removing sequential instance u0.wb_dat_o[6] of view:PrimLib.dff(prim) because there are no references to its outputs 
@W: BN116 :"c:\actelprj\pwm\hdl\pwm.v":95:0:95:5|Removing sequential instance u0.wb_dat_o[5] of view:PrimLib.dff(prim) because there are no references to its outputs 
@W: BN116 :"c:\actelprj\pwm\hdl\pwm.v":95:0:95:5|Removing sequential instance u0.wb_dat_o[4] of view:PrimLib.dff(prim) because there are no references to its outputs 
@W: BN116 :"c:\actelprj\pwm\hdl\pwm.v":95:0:95:5|Removing sequential instance u0.wb_dat_o[3] of view:PrimLib.dff(prim) because there are no references to its outputs 
@W: BN116 :"c:\actelprj\pwm\hdl\pwm.v":95:0:95:5|Removing sequential instance u0.wb_dat_o[2] of view:PrimLib.dff(prim) because there are no references to its outputs 
@W: BN116 :"c:\actelprj\pwm\hdl\pwm.v":95:0:95:5|Removing sequential instance u0.wb_dat_o[1] of view:PrimLib.dff(prim) because there are no references to its outputs 
@W: BN116 :"c:\actelprj\pwm\hdl\pwm.v":95:0:95:5|Removing sequential instance u0.wb_dat_o[0] of view:PrimLib.dff(prim) because there are no references to its outputs 

Finished gated-clock and generated-clock conversion (Time elapsed 0h:00m:01s; Memory used current: 45MB peak: 45MB)

Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:01s; Memory used current: 45MB peak: 46MB)

Starting Early Timing Optimization (Time elapsed 0h:00m:01s; Memory used current: 45MB peak: 46MB)

Finished Early Timing Optimization (Time elapsed 0h:00m:01s; Memory used current: 45MB peak: 46MB)

Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:02s; Memory used current: 45MB peak: 46MB)

Finished preparing to map (Time elapsed 0h:00m:02s; Memory used current: 46MB peak: 47MB)

High Fanout Net Report
**********************

Driver Instance / Pin Name     Fanout, notes                   
---------------------------------------------------------------
u2.addr[0] / Q                 13                              
u2.addr[1] / Q                 13                              
u0.un1_counter_0.I_248 / Y     32                              
rst_pad / Y                    123 : 123 asynchronous set/reset
===============================================================

Promoting Net rst_c on CLKINT  I_6
Replicating u0.un1_counter, fanout 32 segments 3
Buffering u2.clk1m, fanout 21 segments 2
Replicating addr[1], fanout 13 segments 2
Replicating addr[0], fanout 13 segments 2

Finished technology mapping (Time elapsed 0h:00m:02s; Memory used current: 45MB peak: 47MB)

Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:02s; Memory used current: 45MB peak: 47MB)
Replicating u2.clk1m_0, fanout 13 segments 2

Added 1 Buffers
Added 5 Cells via replication

Finished restoring hierarchy (Time elapsed 0h:00m:02s; Memory used current: 45MB peak: 47MB)
Writing Analyst data base C:\Actelprj\PWM\synthesis\top.srm
@N: BN225 |Writing default property annotation file C:\Actelprj\PWM\synthesis\top.map.
Writing EDIF Netlist and constraint files
Found clock top|CLK48M with period 10.00ns 
Found clock top|u1.GLA_inferred_clock with period 10.00ns 
Found clock control|clk1m_inferred_clock with period 10.00ns 


##### START OF TIMING REPORT #####[
# Timing Report written on Thu Sep 27 09:13:37 2007
#


Top view:               top
Library name:           fusion
Operating conditions:   COMWC-2 ( T = 70.0, V = 1.58, P = 1.15, tree_type = balanced_tree )
Requested Frequency:    100.0 MHz
Wire load mode:         top
Wire load model:        fusion
Paths requested:        5
Constraint File(s):    C:\Actelprj\PWM\constraint\top_sdc.sdc
                       
@N: MT195 |This timing report estimates place and route data. Please look at the place and route timing report for final timing..

@N: MT197 |Clock constraints cover only FF-to-FF paths associated with the clock..



Performance Summary 
*******************


Worst slack in design: -1.890

                                 Requested     Estimated     Requested     Estimated                Clock        Clock              
Starting Clock                   Frequency     Frequency     Period        Period        Slack      Type         Group              
------------------------------------------------------------------------------------------------------------------------------------
control|clk1m_inferred_clock     100.0 MHz     84.1 MHz      10.000        11.890        -1.890     inferred     Inferred_clkgroup_0
top|CLK48M                       100.0 MHz     203.2 MHz     10.000        4.921         5.079      inferred     Inferred_clkgroup_1
top|u1.GLA_inferred_clock        100.0 MHz     86.2 MHz      10.000        11.594        -1.594     inferred     Inferred_clkgroup_2
====================================================================================================================================





Clock Relationships
*******************

Clocks                                                      |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
---------------------------------------------------------------------------------------------------------------------------------------------------
Starting                      Ending                        |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
---------------------------------------------------------------------------------------------------------------------------------------------------
control|clk1m_inferred_clock  control|clk1m_inferred_clock  |  10.000      -1.890  |  No paths    -      |  No paths    -      |  No paths    -    
control|clk1m_inferred_clock  top|u1.GLA_inferred_clock     |  Diff grp    -       |  No paths    -      |  No paths    -      |  No paths    -    
top|CLK48M                    top|CLK48M                    |  10.000      5.079   |  No paths    -      |  No paths    -      |  No paths    -    
top|u1.GLA_inferred_clock     top|u1.GLA_inferred_clock     |  10.000      -1.594  |  No paths    -      |  No paths    -      |  No paths    -    
===================================================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************

		No IO constraint found 



====================================
Detailed Report for Clock: control|clk1m_inferred_clock
====================================



Starting Points with Worst Slack
********************************

                 Starting                                                          Arrival           
Instance         Reference                        Type       Pin     Net           Time        Slack 
                 Clock                                                                               
-----------------------------------------------------------------------------------------------------
u2.status[0]     control|clk1m_inferred_clock     DFN1C1     Q       status[0]     0.476       -1.890
u2.status[1]     control|clk1m_inferred_clock     DFN1C1     Q       status[1]     0.476       -1.401
u2.addr[2]       control|clk1m_inferred_clock     DFN1C1     Q       addr[2]       0.476       -1.155
u2.addr_0[0]     control|clk1m_inferred_clock     DFN1C1     Q       addr_0[0]     0.476       -0.895
u2.addr[1]       control|clk1m_inferred_clock     DFN1C1     Q       addr[1]       0.476       -0.811
u2.addr[0]       control|clk1m_inferred_clock     DFN1C1     Q       addr[0]       0.476       -0.469
u2.cou[2]        control|clk1m_inferred_clock     DFN1C1     Q       cou[2]        0.476       0.211 
u2.cou[4]        control|clk1m_inferred_clock     DFN1C1     Q       cou[4]        0.476       0.393 
u2.cou[0]        control|clk1m_inferred_clock     DFN1C1     Q       cou[0]        0.476       0.545 
u2.cou[3]        control|clk1m_inferred_clock     DFN1C1     Q       cou[3]        0.476       0.558 
=====================================================================================================