top_drc.rpt

Core_PWM,verilog语言编写

=====================================================================
Parameters used to run compile:
===============================

Family      : Fusion
Device      : AFS600
Package     : 256 FBGA
Source      : C:\Actelprj\PWM\synthesis\top.edn
Format      : EDIF
Topcell     : top
Speed grade : -2
Temp        : 0:25:70
Voltage     : 1.58:1.50:1.42

Keep Existing Physical Constraints : No
Keep Existing Timing Constraints   : Yes

pdc_abort_on_error                 : Yes
pdc_eco_display_unmatched_objects  : No
pdc_eco_max_warnings               : 10000

demote_globals                     : No
promote_globals                    : No
localclock_max_shared_instances    : 12
localclock_buffer_tree_max_fanout  : 12

combine_register                   : No
delete_buffer_tree                 : No

report_high_fanout_nets_limit      : 10

=====================================================================
Compile starts ...

Warning: CMP201: Net: u1/Core_GLB is floating
Warning: CMP201: Net: u1/Core_GLC is floating
Warning: CMP201: Net: u1/Core_LOCK is floating
Warning: CMP201: Net: u1/Core_YB is floating
Warning: CMP201: Net: u1/Core_YC is floating

Netlist Optimization Report
===========================

Optimized macros:
  - Dangling net drivers:   0
  - Buffers:                1
  - Inverters:              0
  - Tieoff:                 0
  - Logic combining:        47

    Total macros optimized  48

There were 0 error(s) and 5 warning(s) in this design.
=====================================================================
Compile report:
===============

    CORE                     Used:    565  Total:  13824   (4.09%)
    IO (W/ clocks)           Used:      4  Total:    119   (3.36%)
    Differential IO          Used:      0  Total:     58   (0.00%)
    GLOBAL (Chip+Quadrant)   Used:      2  Total:     18   (11.11%)
    PLL                      Used:      1  Total:      2   (50.00%)
    RAM/FIFO                 Used:      0  Total:     24   (0.00%)
    Low Static ICC           Used:      0  Total:      1   (0.00%)
    FlashROM                 Used:      0  Total:      1   (0.00%)
    User JTAG                Used:      0  Total:      1   (0.00%)
    RC oscillator            Used:      0  Total:      1   (0.00%)
    XTL oscillator           Used:      0  Total:      1   (0.00%)
    NVM                      Used:      0  Total:      2   (0.00%)
    AB                       Used:      0  Total:      1   (0.00%)
    AnalogIO                 Used:      0  Total:     46   (0.00%)
    VRPSM                    Used:      0  Total:      1   (0.00%)
    No-Glitch MUX            Used:      0  Total:      2   (0.00%)

Global Information:

    Type            | Used   | Total
    ----------------|--------|-------------
    Chip global     | 2      | 6  (33.33%)
    Quadrant global | 0      | 12 (0.00%)

Core Information:

    Type    | Instances    | Core tiles
    --------|--------------|-----------
    COMB    | 442          | 442
    SEQ     | 123          | 123

I/O Function:

    Type                          | w/o register  | w/ register  | w/ DDR register
    ------------------------------|---------------|--------------|----------------
    Input I/O                     | 2             | 0            | 0
    Output I/O                    | 2             | 0            | 0
    Bidirectional I/O             | 0             | 0            | 0
    Differential Input I/O Pairs  | 0             | 0            | 0
    Differential Output I/O Pairs | 0             | 0            | 0

I/O Technology:

                                    |   Voltages    |             I/Os
    --------------------------------|-------|-------|-------|--------|--------------
    I/O Standard(s)                 | Vcci  | Vref  | Input | Output | Bidirectional
    --------------------------------|-------|-------|-------|--------|--------------
    LVTTL                           | 3.30v | N/A   | 2     | 2      | 0

Net information report:
=======================

The following nets have been assigned to a chip global resource:
    Fanout  Type          Name
    --------------------------
    123     SET/RESET_NET Net   : rst_c
                          Driver: I_6/U_CLKSRC
                          Source: NETLIST
    98      CLK_NET       Net   : GLA
                          Driver: u1/Core
                          Source: ESSENTIAL

High fanout nets in the post compile netlist:
    Fanout  Type          Name
    --------------------------
    12      INT_NET       Net   : addr[0]
                          Driver: u2/addr[0]
    12      INT_NET       Net   : addr[1]
                          Driver: u2/addr[1]
    12      INT_NET       Net   : u0/counter[18]
                          Driver: u0/counter[18]
    11      INT_NET       Net   : u0/I_248_1
                          Driver: u0/un1_counter_0_I_248_1
    11      INT_NET       Net   : u0/I_248_0
                          Driver: u0/un1_counter_0_I_248_0
    11      INT_NET       Net   : u0/counter[16]
                          Driver: u0/counter[16]
    11      INT_NET       Net   : u0/counter[25]
                          Driver: u0/counter[25]
    11      INT_NET       Net   : u0/counter[28]
                          Driver: u0/counter[28]
    11      CLK_NET       Net   : u2/clk1m_0
                          Driver: u2/clk1m_inferred_clock_0
    11      CLK_NET       Net   : u2/clk1m
                          Driver: u2/clk1m

Nets that are candidates for clock assignment and the resulting fanout:
    Fanout  Type          Name
    --------------------------
    21      CLK_NET       Net   : u2/clk1m
                          Driver: u2/clk1m
    12      INT_NET       Net   : addr[0]
                          Driver: u2/addr[0]
    12      INT_NET       Net   : addr[1]
                          Driver: u2/addr[1]
    12      INT_NET       Net   : u0/counter[18]
                          Driver: u0/counter[18]
    11      INT_NET       Net   : u0/I_248_1
                          Driver: u0/un1_counter_0_I_248_1
    11      INT_NET       Net   : u0/I_248_0
                          Driver: u0/un1_counter_0_I_248_0
    11      INT_NET       Net   : u0/counter[16]
                          Driver: u0/counter[16]
    11      INT_NET       Net   : u0/counter[25]
                          Driver: u0/counter[25]
    11      INT_NET       Net   : u0/counter[28]
                          Driver: u0/counter[28]
    10      INT_NET       Net   : addr[2]
                          Driver: u2/addr[2]


SDC Import: Starting final constraints validation...


The Compile command succeeded ( 00:00:01 )