control_drc.rpt

Core_PWM,verilog语言编写

=====================================================================
Parameters used to run compile:
===============================

Family      : Fusion
Device      : AFS600
Package     : 256 FBGA
Source      : C:\Actelprj\PWM\synthesis\control.edn
Format      : EDIF
Topcell     : control
Speed grade : -2
Temp        : 0:25:70
Voltage     : 1.58:1.50:1.42

Keep Existing Physical Constraints : No
Keep Existing Timing Constraints   : Yes

pdc_abort_on_error                 : Yes
pdc_eco_display_unmatched_objects  : No
pdc_eco_max_warnings               : 10000

demote_globals                     : No
promote_globals                    : No
localclock_max_shared_instances    : 12
localclock_buffer_tree_max_fanout  : 12

combine_register                   : No
delete_buffer_tree                 : No

report_high_fanout_nets_limit      : 10

=====================================================================
Compile starts ...


Netlist Optimization Report
===========================

Optimized macros:
  - Dangling net drivers:   0
  - Buffers:                0
  - Inverters:              0
  - Tieoff:                 0
  - Logic combining:        5

    Total macros optimized  5

There were 0 error(s) and 0 warning(s) in this design.
=====================================================================
Compile report:
===============

    CORE                     Used:    417  Total:  13824   (3.02%)
    IO (W/ clocks)           Used:     19  Total:    119   (15.97%)
    Differential IO          Used:      0  Total:     58   (0.00%)
    GLOBAL (Chip+Quadrant)   Used:      2  Total:     18   (11.11%)
    PLL                      Used:      0  Total:      2   (0.00%)
    RAM/FIFO                 Used:      0  Total:     24   (0.00%)
    Low Static ICC           Used:      0  Total:      1   (0.00%)
    FlashROM                 Used:      0  Total:      1   (0.00%)
    User JTAG                Used:      0  Total:      1   (0.00%)
    RC oscillator            Used:      0  Total:      1   (0.00%)
    XTL oscillator           Used:      0  Total:      1   (0.00%)
    NVM                      Used:      0  Total:      2   (0.00%)
    AB                       Used:      0  Total:      1   (0.00%)
    AnalogIO                 Used:      0  Total:     46   (0.00%)
    VRPSM                    Used:      0  Total:      1   (0.00%)
    No-Glitch MUX            Used:      0  Total:      2   (0.00%)

Global Information:

    Type            | Used   | Total
    ----------------|--------|-------------
    Chip global     | 2      | 6  (33.33%)
    Quadrant global | 0      | 12 (0.00%)

Core Information:

    Type    | Instances    | Core tiles
    --------|--------------|-----------
    COMB    | 303          | 303
    SEQ     | 114          | 114

I/O Function:

    Type                          | w/o register  | w/ register  | w/ DDR register
    ------------------------------|---------------|--------------|----------------
    Input I/O                     | 5             | 0            | 0
    Output I/O                    | 14            | 0            | 0
    Bidirectional I/O             | 0             | 0            | 0
    Differential Input I/O Pairs  | 0             | 0            | 0
    Differential Output I/O Pairs | 0             | 0            | 0

I/O Technology:

                                    |   Voltages    |             I/Os
    --------------------------------|-------|-------|-------|--------|--------------
    I/O Standard(s)                 | Vcci  | Vref  | Input | Output | Bidirectional
    --------------------------------|-------|-------|-------|--------|--------------
    LVTTL                           | 3.30v | N/A   | 5     | 14     | 0

Net information report:
=======================

The following nets have been assigned to a chip global resource:
    Fanout  Type          Name
    --------------------------
    114     SET/RESET_NET Net   : rst_c
                          Driver: rst_pad
                          Source: NETLIST
    65      CLK_NET       Net   : count[23]
                          Driver: count_inferred_clock[23]/U_CLKSRC
                          Source: NETLIST

High fanout nets in the post compile netlist:
    Fanout  Type          Name
    --------------------------
    12      CLK_NET       Net   : count[21]
                          Driver: count[21]
    12      CLK_NET       Net   : CLK48M_c
                          Driver: CLK48M_pad
    12      INT_NET       Net   : LED_c_c[1]
                          Driver: addr_1[1]
    12      INT_NET       Net   : LED_c_c_0[1]
                          Driver: addr_1_0[1]
    11      CLK_NET       Net   : count[20]
                          Driver: count[20]
    11      CLK_NET       Net   : CLK48M_c_0
                          Driver: CLK48M_pad_0
    11      CLK_NET       Net   : CLK48M_c_1
                          Driver: CLK48M_pad_1
    10      INT_NET       Net   : LED_c_c[0]
                          Driver: addr_1[0]
    10      INT_NET       Net   : LED_c_c_0[2]
                          Driver: addr_1_0[2]
    10      INT_NET       Net   : LED_c_c_1[2]
                          Driver: addr_1_1[2]

Nets that are candidates for clock assignment and the resulting fanout:
    Fanout  Type          Name
    --------------------------
    32      CLK_NET       Net   : CLK48M_c
                          Driver: CLK48M_pad
    12      CLK_NET       Net   : count[21]
                          Driver: count[21]
    12      INT_NET       Net   : LED_c_c[1]
                          Driver: addr_1[1]
    12      INT_NET       Net   : LED_c_c_0[1]
                          Driver: addr_1_0[1]
    11      CLK_NET       Net   : count[20]
                          Driver: count[20]
    10      INT_NET       Net   : LED_c_c[0]
                          Driver: addr_1[0]
    10      INT_NET       Net   : LED_c_c_0[2]
                          Driver: addr_1_0[2]
    10      INT_NET       Net   : LED_c_c_1[2]
                          Driver: addr_1_1[2]
    10      INT_NET       Net   : LED_c_c_2[2]
                          Driver: addr_1_2[2]
    10      INT_NET       Net   : LED_c_c_0[0]
                          Driver: addr_1_0[0]


SDC Import: Starting final constraints validation...


The Compile command succeeded ( 00:00:01 )