top_syn.prd

来自「Core_PWM,verilog语言编写」· PRD 代码 · 共 14 行

#-- Synplicity, Inc.
#-- Version Synplify Pro 8.6.2H
#-- Project file C:\Actelprj\PWM\synthesis\top_syn.prd
#-- Written on Tue Sep 25 08:56:36 2007

#
### Watch Implementation type ###
#
watch_impl -all
#
### Watch Implementation properties ###
#
watch_prop -clear