control_syn.prj

Core_PWM,verilog语言编写

#add_file options
add_file -verilog "E:/实验例程/高级实验/PWM/Project/PWM/hdl/PWM_contr.v"

#device options
set_option -technology Fusion
set_option -part AFS600

#compilation/mapping options
set_option -symbolic_fsm_compiler true

#compilation/mapping options
set_option -frequency 100.000

#simulation options
impl -active "synthesis"
project -result_file "E:/实验例程/高级实验/PWM/Project/PWM/synthesis/control.edn"