control.srs

Core_PWM,verilog语言编写

@E
@ 
#
#
#
# Created by Synplify Verilog HDL Compiler version 3.7, Build 090R from Synplicity, Inc.
# Copyright 1994-2006 Synplicity, Inc. , All rights reserved.
# Synthesis Netlist written on Tue Sep 25 08:33:04 2007
#
#
#OPTIONS:"|-fixsmult|-I|C:\\Actelprj\\PWM\\synthesis\\|-I|D:\\Libero\\Synplify\\Synplify_862H\\lib|-v95|-devicelib|D:\\Libero\\Synplify\\Synplify_862H\\lib\\proasic\\fusion.v|-autosm|-fid2|-sharing|on|-encrypt|-ui|-pro|-ram|-ll|2000"
#CUR:"D:\\Libero\\Synplify\\Synplify_862H\\bin\\c_ver.exe":1163762892
#CUR:"D:\\Libero\\Synplify\\Synplify_862H\\lib\\proasic\\fusion.v":1149579214
#CUR:"C:\\Actelprj\\PWM\\hdl\\PWM_contr.v":1190627227
f "D:\Libero\Synplify\Synplify_862H\lib\proasic\fusion.v"; # file 0
af .is_verilog 1;
f "C:\Actelprj\PWM\hdl\PWM_contr.v"; # file 1
af .is_verilog 1;
@E
@ 
ftell;
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;