top.msg

Core_PWM,verilog语言编写

@TM:1190680799
@W: BN153 :"":0:0:0:-1|View "prim", Cell "NGMUX", Port "CLK0": remove clock marking
@W: BN153 :"":0:0:0:-1|View "prim", Cell "NGMUX", Port "CLK1": remove clock marking
@W: BN154 :"":0:0:0:-1|View "prim" of Cell "NGMUX": 4 sequential timing arcs are removed
@N: BN225 :"":0:0:0:-1|Writing default property annotation file C:\Actelprj\PWM\synthesis\top.map.
@N: MF249 :"":0:0:0:-1|Running in 32-bit mode.
@N: MF258 :"":0:0:0:-1|Gated clock conversion disabled 
@N: MT195 :"":0:0:0:-1|This timing report estimates place and route data. Please look at the place and route timing report for final timing..
@N: MT197 :"":0:0:0:-1|Clock constraints cover only FF-to-FF paths associated with the clock..
@N: CG364 :"c:\actelprj\pwm\hdl\pwm.v":2:7:2:9|Synthesizing module PWM
@N: MF179 :"c:\actelprj\pwm\hdl\pwm.v":25:6:25:31|M
@N: MF238 :"c:\actelprj\pwm\hdl\pwm.v":28:14:28:25|M
@N: MF179 :"c:\actelprj\pwm\hdl\pwm.v":38:6:38:29|M
@W: BN116 :"c:\actelprj\pwm\hdl\pwm.v":95:0:95:5|M
@N: CG364 :"c:\actelprj\pwm\hdl\pwm_contr.v":2:7:2:13|Synthesizing module control
@TM:1190707635
@W: CG133 :"c:\actelprj\pwm\hdl\pwm_contr.v":15:12:15:15|M
@W: CG133 :"c:\actelprj\pwm\hdl\pwm_contr.v":15:17:15:20|M
@W: CG133 :"c:\actelprj\pwm\hdl\pwm_contr.v":15:22:15:25|M
@W: CG133 :"c:\actelprj\pwm\hdl\pwm_contr.v":17:12:17:16|M
@W: CG133 :"c:\actelprj\pwm\hdl\pwm_contr.v":17:18:17:22|M
@W: CG360 :"c:\actelprj\pwm\hdl\pwm_contr.v":24:16:24:22|M
@N: MF238 :"c:\actelprj\pwm\hdl\pwm_contr.v":48:17:48:26|M
@N: CL201 :"c:\actelprj\pwm\hdl\pwm_contr.v":52:0:52:5|M
@TM:1190680799
@N: CG364 :"c:\actelprj\pwm\hdl\top.v":2:7:2:9|Synthesizing module top
@TM:1190707669
@W: CS148 :"c:\actelprj\pwm\hdl\top.v":24:8:24:9|M
@TM:1190680799
@N: CG364 :"c:\actelprj\pwm\smartgen\pll_1\pll_1.v":5:7:5:11|Synthesizing module PLL_1
@TM:1190705752
@N: CG364 :"d:\libero\synplify\synplify_862h\lib\proasic\fusion.v":260:7:260:12|Synthesizing module PLLINT
@N: CG364 :"d:\libero\synplify\synplify_862h\lib\proasic\fusion.v":1224:7:1224:9|Synthesizing module GND
@N: CG364 :"d:\libero\synplify\synplify_862h\lib\proasic\fusion.v":2043:7:2043:9|Synthesizing module VCC
@N: CG364 :"d:\libero\synplify\synplify_862h\lib\proasic\fusion.v":2974:7:2974:9|Synthesizing module PLL