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Core_PWM,verilog语言编写

@P:  Worst Slack : -1.890
@P:  control|clk1m_inferred_clock - Estimated Frequency : 84.1 MHz
@P:  control|clk1m_inferred_clock - Requested Frequency : 100.0 MHz
@P:  control|clk1m_inferred_clock - Estimated Period : 11.890
@P:  control|clk1m_inferred_clock - Requested Period : 10.000
@P:  control|clk1m_inferred_clock - Slack : -1.890
@P:  top|CLK48M - Estimated Frequency : 203.2 MHz
@P:  top|CLK48M - Requested Frequency : 100.0 MHz
@P:  top|CLK48M - Estimated Period : 4.921
@P:  top|CLK48M - Requested Period : 10.000
@P:  top|CLK48M - Slack : 5.079
@P:  top|u1.GLA_inferred_clock - Estimated Frequency : 86.2 MHz
@P:  top|u1.GLA_inferred_clock - Requested Frequency : 100.0 MHz
@P:  top|u1.GLA_inferred_clock - Estimated Period : 11.594
@P:  top|u1.GLA_inferred_clock - Requested Period : 10.000
@P:  top|u1.GLA_inferred_clock - Slack : -1.594
@P:  Total Area : 613.0
@P:  Total Area : 102.0
@P:  Total Area : 0.0
@P:  Total Area : 511.0
@P:  Total Area : 613.0
@P:  CPU Time : 0h:00m:03s