top.hpj

Core_PWM,verilog语言编写

<!DOCTYPE SimulationProject SYSTEM "hdl-prj.dtd">
<SimulationProject ProductVersion="8.6c" Logfile="top.log" AutoParseProject="1" NameOfComponentToParse="top" Keyfile="verilog.key" Language="Verilog" DelayType="typical" AddTopLevelSignals="0" FileNamesShown="1" HideEmptyLists="1" ShowWatch="1" DumpWatch="0" InteractiveMode="1" ParametersAreWatchable="0" ClearLogBeforeCompile="1" CreateLogFileDuringSim="1" > 
  <FileList>
    <File>C:\Actelprj\PWM\synthesis\top.v</File>
  </FileList>
  <DirList>
    <Directory>C:\Libero\WFL\</Directory>
    <Directory>C:\Actelprj\PWM\hdl</Directory>
  </DirList>
  <LibDirList>
    <Directory>C:\Libero\WFL\lib\verilog\</Directory>
    <Directory>C:\Libero\Designer/lib/vlog/fusion.v</Directory>
  </LibDirList>
  <LibExtensionList>
    <Extension>.v</Extension>
    <Extension>.vo</Extension>
  </LibExtensionList>
</SimulationProject>