top.dsk

Core_PWM,verilog语言编写

<!DOCTYPE Desktop SYSTEM "hdl-prj.dtd">
<Desktop>
  <ProjectWindow Position="0 1 -1 -1 -4 -30 0 0 476 334">
    <Column>84</Column>
  </ProjectWindow>
  <WatchDlg WindowTop="-1" WindowLeft="-1" WindowHeight="0" WindowWidth="0" CaptureLBClick="True" CaptureMouseMove="False" CaptureFromSimulator="True" SelectedTabNum="0">
    <WatchTab InspectedTime="0" ColumnWidth="0">Inspect 1</WatchTab>
    <WatchTab InspectedTime="0" ColumnWidth="0">Inspect 2</WatchTab>
    <WatchTab InspectedTime="0" ColumnWidth="0">Inspect 3</WatchTab>
    <WatchTab InspectedTime="0" ColumnWidth="0">Inspect 4</WatchTab>
    <WatchTab InspectedTime="0" ColumnWidth="0">Inspect 5</WatchTab>
    <WatchTab InspectedTime="0" ColumnWidth="0">Inspect 6</WatchTab>
    <WatchTab InspectedTime="0" ColumnWidth="0">Inspect 7</WatchTab>
  </WatchDlg>
  <TimingDiagram File=".\top_tbench.btim">
    <DiagramWindow X="66" Y="87" W="632" H="202" Maximized="True"></DiagramWindow>
  </TimingDiagram>
</Desktop>