control_tbench.v

Core_PWM,verilog语言编写

// Generated by WaveFormer Lite Version 11.14a at 15:8:24 on 9/25/2007
// Stimulator for stimulus

// Generation Settings:
//   Export type: Stimulus only (reactive export not enabled)
//                Delays, Samples, Markers, etc will not generate code.

// Clock Domains:

//   Unclocked
//   ---------
//     Signals:
//       rst


`define TB_ABORT (3'b000)
`define TB_ONCE (3'b001)
`define TB_DONE (3'b010)
`define TB_LOOPING (3'b011)
`define TB_RESTART (3'b100)
`define TB_END (3'b101)
`timescale  1 ns /  1 ps

module stimulus(CLK48M, rst);
  output CLK48M;
  output rst;
  reg rst_driver;
  assign rst = rst_driver;


  // Control Signal Declarations
  reg [2:0] tb_status;

  // Parm Declarations
  real CLK48M_MinHL;
  real CLK48M_MaxHL;
  real CLK48M_MinLH;
  real CLK48M_MaxLH;
  real CLK48M_JFall;
  real CLK48M_JRise;
  real CLK48M_Duty;
  real CLK48M_Period;
  real CLK48M_Offset;


  // The following initial block will start up the stimulator.
  initial
    begin
    AssignParms;
    tb_status <= `TB_ONCE;
    Unclocked;
    tb_status <= `TB_DONE;
    $display("Note: At %t: End of stimulus reached.  Use End Diagram Marker to extend or shorten stimulus.", $time);
    end

  // Parm Assignment Task
  task AssignParms;
    begin
    CLK48M_MinHL = 0.0;
    CLK48M_MaxHL = 0.0;
    CLK48M_MinLH = 0.0;
    CLK48M_MaxLH = 0.0;
    CLK48M_JFall = 0.0;
    CLK48M_JRise = 0.0;
    CLK48M_Duty = 50.0;
    CLK48M_Period = 20.833;
    CLK48M_Offset = 0.0;
    end
  endtask

  // Clocks

  // Clock Instantiation
  wire [63:0] CLK48M_Offset_bits = $realtobits(CLK48M_Offset);
  wire [63:0] CLK48M_Period_bits = $realtobits(CLK48M_Period);
  wire [63:0] CLK48M_Duty_bits = $realtobits(CLK48M_Duty);
  wire [63:0] CLK48M_JRise_bits = $realtobits(CLK48M_JRise);
  wire [63:0] CLK48M_JFall_bits = $realtobits(CLK48M_JFall);
  wire [63:0] CLK48M_MinLH_bits = $realtobits(CLK48M_MinLH);
  wire [63:0] CLK48M_MaxLH_bits = $realtobits(CLK48M_MaxLH);
  wire [63:0] CLK48M_MinHL_bits = $realtobits(CLK48M_MinHL);
  wire [63:0] CLK48M_MaxHL_bits = $realtobits(CLK48M_MaxHL);
  tb_clock_minmax #(1) tb_CLK48M(tb_status[1:0],
            CLK48M,
            CLK48M_Offset_bits,
            CLK48M_Period_bits,
            CLK48M_Duty_bits,
            CLK48M_MinLH_bits,
            CLK48M_MaxLH_bits,
            CLK48M_MinHL_bits,
            CLK48M_MaxHL_bits,
            CLK48M_JRise_bits,
            CLK48M_JFall_bits);

  // Clocked Sequences

  // Sequence: Unclocked

  // Drive signals to their initial values
  initial
    begin
    rst_driver <= 1'b0;
    end

  task Unclocked;
    begin
    #4194;
    rst_driver <= 1'b1;
    #7602;
    rst_driver <= 1'b0;
    #1546176431;
    end
  endtask
endmodule

// Clock models used by diagram.

// Copied contents of file: C:\Libero\WFL\lib\verilog\tb_clock_minmax.v

module tb_clock_minmax(tb_status, CLK, offset_bits, period_bits, duty_bits, minLH_bits, maxLH_bits, minHL_bits, maxHL_bits, jRise_bits, jFall_bits);
  parameter initialize = 0;

  input [1:0] tb_status;
  output CLK;
  input [63:0] offset_bits;
  input [63:0] period_bits;
  input [63:0] duty_bits;
  input [63:0] minLH_bits;
  input [63:0] maxLH_bits;
  input [63:0] minHL_bits;
  input [63:0] maxHL_bits;
  input [63:0] jRise_bits;
  input [63:0] jFall_bits;

  reg  CLK;
  real offset;
  real period;
  real duty;
  real minLH;
  real maxLH;
  real minHL;
  real maxHL;
  real jRise;
  real jFall;
  real CLK_high;
  real CLK_low;
 
  task DriveLHInvalidRegion;
    begin
    if ( (jRise + maxLH - minLH) > 0.0 )
      begin
      CLK <= 1'bx;
      #((jRise + maxLH - minLH));
      end
    end
  endtask

  task DriveHLInvalidRegion;
    begin
    if ( (jFall + maxHL - minHL) > 0.0 )
      begin
      CLK <= 1'bx;
      #((jFall + maxHL - minHL));
      end
    end
  endtask

  always
    begin
    @(posedge tb_status[0])
    offset = $bitstoreal( offset_bits );
    period = $bitstoreal( period_bits );
    duty  = $bitstoreal( duty_bits );
    minLH = $bitstoreal( minLH_bits );
    maxLH = $bitstoreal( maxLH_bits );
    minHL = $bitstoreal( minHL_bits );
    maxHL = $bitstoreal( maxHL_bits );
    jRise = $bitstoreal( jRise_bits );
    jFall = $bitstoreal( jFall_bits );
    if (period <= 0.0)
      $display("Error: Period for clock %m is invalid (period=%f).  Clock will not be driven", period);
    else if (duty <= 0.0)
      $display("Error: Duty for clock %m is invalid (duty=%f).  Clock will not be driven", duty);
    else
      begin
      CLK_high = period * duty / 100;
      CLK_low = period - CLK_high;
      
      if ( (offset + (minLH - jRise/2)) >= 0.0 )
        begin
        if (initialize)
          CLK <= 1'b0; // drive initial state
        #(offset + (minLH - jRise/2))
        ;
        end
      else
        begin // wait for x
        if (initialize)
          CLK <= 1'bx; // in middle of X region, init to X
        #((jRise/2 + maxLH) + (offset))
        CLK <= 1'b1;
        #((CLK_high - (maxLH + jRise/2) + (minHL - jFall/2)))
        DriveHLInvalidRegion;
        CLK <= 1'b0;
        #((CLK_low - (maxHL + jFall/2) + (minLH - jRise/2)))
        ;
        end
  
      while ( tb_status[0] == 1'b1 )
        begin : clock_loop
        DriveLHInvalidRegion;
        CLK <= 1'b1;
        #((CLK_high - (maxLH + jRise/2) + (minHL - jFall/2)))
        DriveHLInvalidRegion;
        CLK <= 1'b0;
        #((CLK_low - (maxHL + jFall/2) + (minLH - jRise/2)))
        ;
        end
      end
    end
endmodule

// End of contents of file: C:\Libero\WFL\lib\verilog\tb_clock_minmax.v

// Test Bench wrapper for stimulus and Model Under Test

module testbench;
  wire CLK48M;
  wire rst;
  wire [2:0] addr;
  wire [7:0] data;
  wire CS;
  wire WE;

  // Stimulator instance
  stimulus stimulus_0(.CLK48M(CLK48M),
            .rst(rst));

  // Instantiation of Model Under Test.
  control control_0(.CLK48M(CLK48M),
            .rst(rst),
            .addr(addr),
            .data(data),
            .CS(CS),
            .WE(WE));
endmodule