modelsim.ini.sav

来自「Core_PWM,verilog语言编写」· SAV 代码 · 共 30 行

[Library]
others = $MODEL_TECH/../modelsim.ini
fusion = $MODEL_TECH/../actel/vlog/fusion



presynth = presynth

postsynth = postsynth


postlayout = ../designer/impl1/simulation/postlayout










syncad_vhdl_lib = C:\Libero8.1\Designer/lib/actel/syncad_vhdl_lib

[vcom]
VHDL93 = 1

[vsim]
IterationLimit = 5000