run.do

Core_PWM,verilog语言编写

quietly set ACTELLIBNAME fusion
quietly set PROJECT_DIR "C:/Actelprj/PWM"
vlib presynth
vmap fusion "$env(MODEL_TECH)/../actel/vlog/fusion"
vmap presynth presynth
vlog "+incdir+${PROJECT_DIR}/hdl" "+incdir+${PROJECT_DIR}/hdl" -work presynth "${PROJECT_DIR}/hdl/PWM_contr.v"
vlog "+incdir+${PROJECT_DIR}/stimulus" "+incdir+${PROJECT_DIR}/hdl" -work presynth "${PROJECT_DIR}/stimulus/control_tbench.v"
vsim -L fusion -L presynth  -t 1ps presynth.testbench
add wave /testbench/*
run 1000ns