_primary.vhd

来自「Core_PWM,verilog语言编写」· VHDL 代码 · 共 21 行

library verilog;
use verilog.vl_types.all;
entity control is
    generic(
        div_r           : integer := 999;
        cyc_r           : integer := 249;
        init_pwm        : integer := 1;
        w_div           : integer := 2;
        w_cyc           : integer := 4;
        idle            : integer := 8
    );
    port(
        CLK48M          : in     vl_logic;
        rst             : in     vl_logic;
        addr            : out    vl_logic_vector(2 downto 0);
        data            : out    vl_logic_vector(7 downto 0);
        CS              : out    vl_logic;
        WE              : out    vl_logic
    );
end control;