_primary.vhd

Core_PWM,verilog语言编写

library verilog;
use verilog.vl_types.all;
entity PWM is
    port(
        data            : in     vl_logic_vector(7 downto 0);
        addr            : in     vl_logic_vector(2 downto 0);
        rst_c           : in     vl_logic;
        GLA             : in     vl_logic;
        pwmout_c        : out    vl_logic;
        N_261           : in     vl_logic;
        WE              : in     vl_logic;
        CS              : in     vl_logic;
        N_108           : in     vl_logic
    );
end PWM;