_primary.vhd

来自「Core_PWM,verilog语言编写」· VHDL 代码 · 共 9 行

library verilog;
use verilog.vl_types.all;
entity stimulus is
    port(
        CLK48M          : out    vl_logic;
        rst             : out    vl_logic
    );
end stimulus;