_info

来自「Core_PWM,verilog语言编写」· 代码 · 共 91 行

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91 行
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m25513cModel TechnologydC:\Actelprj\PWM\simulationvcontrolI7KRYmmi_SP__?aieE;RHX2V:b82Q9DI0:7dGiUg90hmB0w11907044538C:/Actelprj/PWM/synthesis/top.vFC:/Actelprj/PWM/synthesis/top.vL0 1345V:b82Q9DI0:7dGiUg90hmB0OW;L;6.2g;35r131o+incdir+C:/Actelprj/PWM/synthesis +incdir+C:/Actelprj/PWM/hdl -work postsynth -O0vPLL_1ID5XJW]Nf:SSQ99@j5DH[V1ViZ26]3Q?K>H2R]H>d`Ume2w11907044538C:/Actelprj/PWM/synthesis/top.vFC:/Actelprj/PWM/synthesis/top.vL0 1583ViZ26]3Q?K>H2R]H>d`Ume2OW;L;6.2g;35r131o+incdir+C:/Actelprj/PWM/synthesis +incdir+C:/Actelprj/PWM/hdl -work postsynth -O0n@p@l@l_1vPWMICY`T<eO[^E2ii@O08AF240VlYb5nM8[=OE5M[5P[z3O<1w11907044538C:/Actelprj/PWM/synthesis/top.vFC:/Actelprj/PWM/synthesis/top.vL0 5VlYb5nM8[=OE5M[5P[z3O<1OW;L;6.2g;35r131o+incdir+C:/Actelprj/PWM/synthesis +incdir+C:/Actelprj/PWM/hdl -work postsynth -O0n@p@w@mvstimulusI6Z3IJg6OZaX=aH`Mcgk4o1VKzS?b2FgGJ4[f]VWXO4Yo3w11907045188C:/Actelprj/PWM/stimulus/top_tbench.vFC:/Actelprj/PWM/stimulus/top_tbench.vL0 24VKzS?b2FgGJ4[f]VWXO4Yo3OW;L;6.2g;35r131o+incdir+C:/Actelprj/PWM/stimulus +incdir+C:/Actelprj/PWM/hdl -work postsynth -O0vtb_clock_minmaxI6=FVZZ`V5LX:JdV[kIQXU1V]<miNJ_R^N1gLiJ7V>ii92w11907045188C:/Actelprj/PWM/stimulus/top_tbench.vFC:/Actelprj/PWM/stimulus/top_tbench.vL0 120V]<miNJ_R^N1gLiJ7V>ii92OW;L;6.2g;35r131o+incdir+C:/Actelprj/PWM/stimulus +incdir+C:/Actelprj/PWM/hdl -work postsynth -O0vtestbenchI6f2eFe;df4@=9RAG4[2@i0VhGfW:390DM[oDMzegDH9`2w11907045188C:/Actelprj/PWM/stimulus/top_tbench.vFC:/Actelprj/PWM/stimulus/top_tbench.vL0 227VhGfW:390DM[oDMzegDH9`2OW;L;6.2g;35r131o+incdir+C:/Actelprj/PWM/stimulus +incdir+C:/Actelprj/PWM/hdl -work postsynth -O0vtopI01;e4kEPZVOH@^7[C=_0T2VSYLh>zmfF5]_lFY_oJLXS1w11907044538C:/Actelprj/PWM/synthesis/top.vFC:/Actelprj/PWM/synthesis/top.vL0 1634VSYLh>zmfF5]_lFY_oJLXS1OW;L;6.2g;35r131o+incdir+C:/Actelprj/PWM/synthesis +incdir+C:/Actelprj/PWM/hdl -work postsynth -O0

_info - 源码说明

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