half_adder.v

来自「是几个用Verilog HDL语言编写的源代码（里面包括实现滤波器等）」· Verilog 代码 · 共 28 行

module half_adder(ina,inb,sum_out,carry_out,clk,rst);

input      ina;
input      inb;
input      clk;
input      rst;

output     sum_out;
output     carry_out;

reg        sum_out;
reg        carry_out;

always @(posedge clk or negedge rst)
begin
  if(!rst)
    begin
      sum_out <= 1'b0;
      carry_out <= 1'b0;
    end
  else
    begin
      sum_out <= ina^inb;
      carry_out <= ina&inb;
    end
end
endmodule