decimation.v

来自「是几个用Verilog HDL语言编写的源代码（里面包括实现滤波器等）」· Verilog 代码 · 共 30 行

module decimation(data_in,clk,rst_n,data_out);

parameter    DATA_WIDTH = 8;

input   [DATA_WIDTH-1:0]   data_in;
input                      clk;
input                      rst_n;

output  [DATA_WIDTH-1:0]   data_out;

reg     [DATA_WIDTH-1:0]   data_out;
reg     [1:0]              count;

always @(posedge clk or negedge rst_n)
begin
  if(!rst_n)
    count <= 0;
  else
    count <= count + 1'b1;
end

always @(posedge clk or negedge rst_n)
begin
  if(!rst_n)
    data_out <= 0;
  else
    if(count==3)
      data_out <= data_in;
end
endmodule