ripple_adder4b.v

是几个用Verilog HDL语言编写的源代码（里面包括实现滤波器等）

module ripple_adder4b(ina,inb,sum_out);

parameter    ADDER_WIDTH = 4;
parameter    SUM_WIDTH = 5;

input  [ADDER_WIDTH-1:0]    ina;
input  [ADDER_WIDTH-1:0]    inb;


output [SUM_WIDTH -1:0]     sum_out;

wire   [ADDER_WIDTH-1:0]    carry_out;
/*
reg                         ina1,inb1;
reg    [1:0]                ina2,inb2;
reg    [2:0]                ina3,inb3;
always @(posedge clk or negedge rst)
begin
  if(!rst)
    begin
      ina1 <= 1'b0;
      inb1 <= 1'b0;
      ina2 <= 2'b00;
      inb2 <= 2'b00;
      ina3 <= 3'b000;
      inb3 <= 3'b000;
    end
  else
    begin
      ina1 <= ina[1];
      inb1 <= inb[1];
      
      ina2[0] <= ina[2];
      ina2[1] <= ina2[0];
      inb2[0] <= inb[2];
      inb2[1] <= inb2[0];
      
      ina3[0] <= ina[3];
      ina3[1] <= ina3[0];
      ina3[2] <= ina3[1];   
      
      inb3[0] <= inb[3];
      inb3[1] <= inb3[0];
      inb3[2] <= inb3[1];
      
    end
end
*/
full_adder u1 (ina[0],inb[0],1'b0,sum_out[0],carry_out[0]);
full_adder u2 (ina[1],inb[1],carry_out[0],sum_out[1],carry_out[1]);
full_adder u3 (ina[2],inb[2],carry_out[1],sum_out[2],carry_out[2]);
full_adder u4 (ina[3],inb[3],carry_out[2],sum_out[3],carry_out[3]);

assign  sum_out[4] = carry_out[3];
endmodule