differentiator.v

来自「是几个用Verilog HDL语言编写的源代码（里面包括实现滤波器等）」· Verilog 代码 · 共 26 行

module differentiator(data_in,hold,clk,rst_n,data_out);

parameter    DATA_WIDTH = 8;

input   [DATA_WIDTH-1:0]   data_in;
input                      hold;
input                      clk;
input                      rst_n;

output  [DATA_WIDTH-1:0]   data_out;

reg     [DATA_WIDTH-1:0]   buffer;

assign data_out = data_in-buffer;

always @(posedge clk or negedge rst_n)
begin
  if(!rst_n)
    buffer <= 0;
  else
    if(hold)
      buffer <= buffer;
    else
      buffer <= data_in;
end
endmodule