pipe_adder8b.v

是几个用Verilog HDL语言编写的源代码（里面包括实现滤波器等）

module pipe_adder8b(ina,inb,sum_out,clk,rst_n);

parameter    ADDER_WIDTH = 8;       
parameter    SUM_WIDTH = 9;
parameter    HALF_ADDER_WIDTH = 4;         
                                    
input  [ADDER_WIDTH-1:0]        ina;    
input  [ADDER_WIDTH-1:0]        inb;    
input                           rst_n;    
input                           clk;    
                                    
output [SUM_WIDTH -1:0]         sum_out;
                                    
reg    [SUM_WIDTH -1:0]         sum_out;
reg    [HALF_ADDER_WIDTH-1:0]   ina_lsb;
reg    [HALF_ADDER_WIDTH-1:0]   ina_msb;
reg    [HALF_ADDER_WIDTH-1:0]   inb_lsb;
reg    [HALF_ADDER_WIDTH-1:0]   inb_msb;
reg    [HALF_ADDER_WIDTH-1:0]   ina_msb1;
reg    [HALF_ADDER_WIDTH-1:0]   inb_msb1;
reg    [HALF_ADDER_WIDTH:0]     sum11;
wire   [HALF_ADDER_WIDTH:0]     sum1;
wire   [HALF_ADDER_WIDTH:0]     sum2;

always @(posedge clk or negedge rst_n)
begin
  if(!rst_n)
    begin
      ina_lsb <= 4'b0000;
      ina_msb <= 4'b0000;
      inb_lsb <= 4'b0000;
      inb_msb <= 4'b0000;
    end
  else
    begin
      ina_lsb <= ina[3:0];
      ina_msb <= ina[7:4];
      inb_lsb <= inb[3:0];
      inb_msb <= inb[7:4];
    end
end

fast_adder4b u1 (ina_lsb,inb_lsb,1'b0,sum1,clk,rst_n);

always @(posedge clk or negedge rst_n) 
begin                                
  if(!rst_n)                           
    begin                            
      ina_msb1 <= 4'b0000;            
      inb_msb1 <= 4'b0000;
    end
  else
    begin
      ina_msb1 <= ina_msb;          
      inb_msb1 <= inb_msb;
    end
end

fast_adder4b u2 (ina_msb1,inb_msb1,sum1[4],sum2,clk,rst_n);

always @(posedge clk or negedge rst_n) 
begin                                
  if(!rst_n)                           
    sum11 <= 4'b0000;
  else
    sum11 <= sum1;
end

always @(posedge clk or negedge rst_n) 
begin                                
  if(!rst_n)                           
    sum_out <= 9'b0000_00000;
  else
    sum_out <= {sum2,sum11[3:0]};
end

endmodule