full_adder.v

来自「是几个用Verilog HDL语言编写的源代码（里面包括实现滤波器等）」· Verilog 代码 · 共 31 行

module full_adder(ina,inb,carry_in,sum_out,carry_out);

input      ina;
input      inb;
input      carry_in;


output     sum_out;
output     carry_out;

//reg        sum_out;
//reg        carry_out;

assign sum_out = (ina^inb)^carry_in;
assign carry_out = (ina&inb)|((ina^inb)&carry_in);
/*
always @(posedge clk or negedge rst)
begin
  if(!rst)
    begin
      sum_out <= 1'b0;
      carry_out <= 1'b0;
    end
  else
    begin
      sum_out <= (ina^inb)^carry_in;
      carry_out <= (ina&inb)|((ina^inb)&carry_in);
    end
end
*/
endmodule