fir.v

是几个用Verilog HDL语言编写的源代码（里面包括实现滤波器等）

module fir(clk,rst_n,fir_in,fir_out);
parameter   IDATA_WIDTH  = 12;                            //input data width
parameter   PDATA_WIDTH  = 13;                            //process data width
parameter   FIR_TAP      = 8;                            //fir tap 
parameter   FIR_TAPHALF  = 4;                            //fir tap half
parameter   COEFF_WIDTH = 12;                             //coff width
parameter   OUT_WIDTH   = 27;                             //output width
      
parameter   cof1        = 12'd41;
parameter   cof2        = 12'd132;
parameter   cof3        = 12'd341;
parameter   cof4        = 12'd510;
      
      
input                      clk;
input                      rst_n;
input   [IDATA_WIDTH-1:0]  fir_in;
output  [OUT_WIDTH-1:0]    fir_out;
      
reg     [OUT_WIDTH-1:0]    fir_out;
      
reg     [IDATA_WIDTH-1:0]  fir_in_reg;
reg     [PDATA_WIDTH-1:0]  shift_buf [FIR_TAP-1:0];      // define 8 shift buffer

wire     [PDATA_WIDTH-1:0]  add07;
wire     [PDATA_WIDTH-1:0]  add16;
wire     [PDATA_WIDTH-1:0]  add25;
wire     [PDATA_WIDTH-1:0]  add34;

wire     [PDATA_WIDTH+COEFF_WIDTH-1:0]  mul1;
wire     [PDATA_WIDTH+COEFF_WIDTH-1:0]  mul2;
wire     [PDATA_WIDTH+COEFF_WIDTH-1:0]  mul3;
wire     [PDATA_WIDTH+COEFF_WIDTH-1:0]  mul4;
integer i,j;
      
always @(posedge clk or negedge rst_n)
begin 
  if(!rst_n)
    fir_in_reg <=12'b0000_0000_0000;
  else
    fir_in_reg <= fir_in;
end   
      
always @(posedge clk or negedge rst_n)
begin 
  if(!rst_n)
    for(i=0;i<=FIR_TAP-1;i=i+1)
        shift_buf[i]<=13'b0000_0000_00000;
  else
    begin
      for(j=0;j<FIR_TAP-1;j=j+1)
        shift_buf[j+1]<=shift_buf[j];
      shift_buf[0]<={fir_in_reg[IDATA_WIDTH-1],fir_in_reg};  //sign expand
    end
end   

assign  add07 = shift_buf[0] + shift_buf[7];
assign  add16 = shift_buf[1] + shift_buf[6];
assign  add25 = shift_buf[2] + shift_buf[5];
assign  add34 = shift_buf[3] + shift_buf[4];

mul12X13 mul1_ins(cof1,add07,mul1);     
mul12X13 mul2_ins(cof2,add16,mul2); 
mul12X13 mul3_ins(cof3,add25,mul3); 
mul12X13 mul4_ins(cof4,add34,mul4); 

wire [25:0] add_mul12 = {mul1[24],mul1} + {mul2[24],mul2};
wire [25:0] add_mul34 = {mul3[24],mul3} + {mul4[24],mul4};
      
always @(posedge clk or negedge rst_n)
begin 
  if(!rst_n)
    fir_out <= 27'b0;
  else
    fir_out <= {add_mul12[25],add_mul12} + {add_mul34[25],add_mul34};
end

endmodule