test_par_fir.v

是几个用Verilog HDL语言编写的源代码（里面包括实现滤波器等）

`define auto_init
`timescale 1ns/1ns
`define INPUT_FILE "datainb.txt"
`define OUTPUT_FILE "data_out.txt"

module test_par_fir();

parameter   NOOFDATA = 400;                            // NO. of data
parameter   IDATA_WIDTH  = 12;                         //input data width
parameter   PDATA_WIDTH  = 13;                         //process data width
parameter   FIR_TAP      = 8;                            //fir tap 
parameter   FIR_TAPHALF  = 4;                           //fir tap half
parameter   COEFF_WIDTH = 12;                          //coff width
parameter   OUT_WIDTH   = 27;                          //output width

parameter CLK_CYCLE = 20;                                                     
parameter CLK_HCYCLE =10;                               // half clock cycle 
//input
reg                      clk;
reg                      rst_n;
reg   [IDATA_WIDTH-1:0]  fir_in;
//output
wire  [OUT_WIDTH-1:0]    fir_out;
//reg
integer regcount;                                                                                                                                                                                                  
reg    [IDATA_WIDTH-1:0] memb [1:NOOFDATA];        // memory used for storing input //file data(binary)
reg    [OUT_WIDTH-1:0] membyte [0:NOOFDATA-1];     // memory used for storing output
reg    write;                                            //write data to file signal
integer count;                                            //write data count signal
integer handle;                                          // file handle
//ins
par_fir  dut(clk,rst_n,fir_in,fir_out); 

                                                                
    // Initialize Inputs                                        
    // Read the data in file into memory                        
    `ifdef auto_init                                            
                                                               
        initial 
          begin                                           
            // NOTE: THE DATA INPUT FILES MUST EXIST            
            $readmemb(`INPUT_FILE,memb);                        
            regcount = 0;
            count = 0; 
            handle = 0;                                                                                               
            clk = 1'b0;                                      
                                                                
	    rst_n=1'b0;                               
            #(10*CLK_CYCLE + CLK_HCYCLE) rst_n=1'b1;                                       
        end                                                     
                                                                
    `endif          

  always #CLK_HCYCLE clk = ~clk;                       //generate clock signal
  
always @(posedge clk or negedge rst_n)                                            
  begin                               
    if(!rst_n)
      begin
        regcount = 0;
        fir_in   <= 12'b0000_0000_0000;
      end
    else
      begin
        regcount = regcount + 1;
        fir_in   <= memb[regcount];                  //input testcase 
        membyte[regcount] <= fir_out;                //output data into memory
      end
  end     

always @(posedge clk or negedge rst_n)                                            
  begin                               
    if(!rst_n)
      write <= 1'b0;
    else
      begin
        if((regcount == NOOFDATA))
          write <= 1'b1;                              //generate write file signal
      end
  end

    // On reaching the end of the file, store the output data memory
    // into file
always@(posedge write)
  begin
    handle = $fopen(`OUTPUT_FILE);
    $display("writing results to file...");
    for (count = 0; count < NOOFDATA; count = count + 1)
    begin
        $fdisplay(handle, "%B", membyte[count]);     //write data to output file
        $display("%B", membyte[count]);
    end
    $fclose(handle);
  end  
endmodule