timectl.v

用FPGA实现带马表日历的电子表

//测量单元测量控制
//timectl.v
//输入1MHz时钟，产生测量开始信号和停止信号
//可以通过对寄存器的读写来改变测量时间
module timectl(rst,clk1mhz,cs,wr_n,ab,din,start,stop,ctlreg);
input 	rst,clk1mhz;
input	cs,wr_n;
input	[1:0]	ab;
input	[7:0]	din;
output	start,stop;
output	[7:0]	ctlreg;

reg		[7:0]	ctlreg;
reg		[23:0]	max;	//计数最大值	
reg		[23:0]	count;	//计数器
reg		start,stop;

	//处理控制寄存器的改变
	always	@(posedge rst or posedge wr_n)
	begin
		if(rst)
			ctlreg<=8'h03;
		else if(cs && (ab==2'b10))
			ctlreg<=din;
	end
	//根据ctlreg生成计数最大值
	always	@(ctlreg)
	begin
		case(ctlreg)
			8'h00:	max<=24'd1000;		//1ms
			8'h01:	max<=24'd10000;		//10ms
			8'h02:	max<=24'd100000;	//100ms
			8'h03:	max<=24'd1000000;	//1000ms
			8'h04:	max<=24'd10000000;	//10000ms
			default:max<='bx;
		endcase
	end
	//根据当前设置产生start和stop信号
	always	@(posedge rst or posedge clk1mhz)
	begin
		if(rst)
			begin
			count<=24'd0;
			start<=0;
			stop<=0;
			end
		else if(count==24'd0)
			begin
			count<=count+1;
			start<=1;
			stop<=0;
			end
		else if(count==max)
			begin
			count<=24'd0;
			start<=0;
			stop<=1;
			end
		else
			begin
			count<=count+1;
			start<=0;
			stop<=0;
			end
	end
endmodule