counter.v

来自「用FPGA实现带马表日历的电子表」· Verilog 代码 · 共 52 行

//测量单元中的计数器模块
//counter.v
//start 信号对计数器清零同时开始一个测量周期
//stop信号锁存测量结果
module counter(rst,signal,start,stop,result,overflow);
input	rst;			//异步复位
input 	signal;			//被测信号作为计数时钟
input 	start,stop;		//时序控制信号
output	[15:0] result;	//测量结果2字节
output 	overflow;		//计数溢出标志

reg	[15:0]	result;
reg	[15:0]	countReg;
reg			overflow;
reg			overflowFlag;
//计数
always	@(posedge rst or posedge start or posedge signal)
begin
	if(rst)
		begin
		countReg<=16'h0000;
		overflowFlag<=0;
		end
	else if(start)
		begin					//计数器归零
		countReg<=16'h0000;
		overflowFlag<=0;
		end
	else if(countReg==16'hffff)
		overflowFlag<=1;		//计数溢出
	else 
		countReg<=countReg+1;
end
//输出计数值
always	@(posedge rst or posedge stop)
begin
	if(rst)
		result<=16'h0000;		
	else
		result<=countReg;
end
//输出溢出标志
always	@(posedge rst or posedge stop)
begin
	if(rst)
		overflow<=0;
	else
		overflow<=overflowFlag;
end

endmodule