top.v

用FPGA实现带马表日历的电子表

//top.v
//顶层文件
module	top(
			lrst_n,mclk,
			la,lad,wr_n,rd_n,	//总线端信号
			sig					//被测信号
			);
input	lrst_n,mclk;			//复位信号和时钟输入(20m)
input	[15:0]	la;
inout	[7:0]	lad;
input	wr_n,rd_n;
input	[3:0]	sig;

wire	[3:0]	cs;
wire	rst,clk1mhz;
wire	[7:0]	out0,out1,out2,out3,out_all;
	
	assign	rst=!lrst_n;	//内部复位信号为高电平有效
	//译码
	decoder	u1(.la(la[15:12]),.cs(cs));
	//时钟分频器输入20m输出1m
	clkgen	u2(.rst(rst),.mclk(mclk),.clk1mhz(clk1mhz));
	//测量单元
	munit	u3(.rst(rst),.clk1mhz(clk1mhz),.cs(cs[0]),.wr_n(wr_n),.ab(la[1:0]),.din(lad),.signal(sig[0]),.out(out0));
	munit	u4(.rst(rst),.clk1mhz(clk1mhz),.cs(cs[1]),.wr_n(wr_n),.ab(la[1:0]),.din(lad),.signal(sig[1]),.out(out1));
	munit	u5(.rst(rst),.clk1mhz(clk1mhz),.cs(cs[2]),.wr_n(wr_n),.ab(la[1:0]),.din(lad),.signal(sig[2]),.out(out2));
	munit	u6(.rst(rst),.clk1mhz(clk1mhz),.cs(cs[3]),.wr_n(wr_n),.ab(la[1:0]),.din(lad),.signal(sig[3]),.out(out3));

	//数据选择器
	datasel u7(.cs(cs),.din0(out0),.din1(out1),.din2(out2),.din3(out3),.dout(out_all));

	//三态控制
	assign	lad=(!rd_n)?out_all:8'hzz;

endmodule