clkgen.v

来自「用FPGA实现带马表日历的电子表」· Verilog 代码 · 共 26 行

//输入20m时钟，输出1m
module clkgen(rst,mclk,clk1mhz);
input	rst,mclk;
output	clk1mhz;

reg	[3:0]	count;
reg			clk1mhz;

	always	@(posedge rst or posedge mclk)
	begin
		if(rst)
			begin
			clk1mhz<=0;
			count<=4'd0;
			end
		else if(count==4'd9)
			begin
			clk1mhz<=!clk1mhz;
			count<=4'd0;
			end
		else	
			count<=count+1;
	end

endmodule