uart_tb.v.svn-base

一个用verilog实现的fpga上的uart接口模块

`timescale 1ns/1ns
module uart_tb;
    
	reg  clk1x,clk16x,rst,s_in,wr;
	reg [7:0] data_in;
	reg [7:0] port;
	wire [7:0] data_out;
	wire s_out;
	wire interrupt;
	uart  uu(s_in,s_out,data_in,data_out,wr,clk1x,clk16x,rst,port,interrupt);
	
	initial
	begin
		clk16x<=0;
		clk1x<=0;
		port<=8'haa;
		wr<=0;
		#32
		rst<=1;
		s_in<=1;
		#32 	rst<=0;
		//transmit 10101101 0 11
		   	data_in<=8'b10101101;
		
		#32 	wr<=1;
		#64	wr<=0;
		
		
		//receive  11101101 1
		#256	s_in<=0;
		#32	s_in<=1;//bit 1
		#32	s_in<=0;//bit 2
		#32	s_in<=1;//bit 3
		#32	s_in<=0;//bit 4
		#32	s_in<=0;//bit 5
		#32	s_in<=0;//bit 6
		#32	s_in<=0;//bit 7
		#32	s_in<=0;//bit 8
		//parity correct
		#32	s_in<=1;
		//end 
		#32 	s_in<=1;
			
	end
	always #1 clk16x = ~clk16x;
	always #16 clk1x = ~clk1x;
    
endmodule