transmit_tb.v.svn-base

一个用verilog实现的fpga上的uart接口模块

`timescale 1ns/1ns
module transmit_tb;
    
    reg clk;
    reg rst,write;
    reg [7:0] data_in;
    reg [7:0] port;
    wire serial_out ;
    wire tx_complete ;
    initial
    begin
        clk <= 0;
        rst <= 0;
        write <=0;
        port<=8'haa;
        #50 rst <=1;
        #1 rst <=0;
        #90 data_in <=115;
        #20 write <= 1;
        #50 write <=0;
        
        #120 write <= 1;
        #90 data_in <=33;
        #50 write <=0;
        #1000 $stop;
    end
    always #1 clk = ~clk;
    transmit m(clk,rst,data_in,write,serial_out,tx_complete,port);
endmodule