test.v.svn-base

来自「一个用verilog实现的fpga上的uart接口模块」· SVN-BASE 代码 · 共 31 行

`timescale 1ns/1ns
module test;
    
reg clk,rst;
reg [7:0]din;
reg wr_en;
wire dout;
    initial
    begin
        clk <= 0;
        rst <= 0;
        wr_en <=0;
        
        #50 rst <=1;
        #10 rst <=0;
        
        #90 din <=115;
        #20 wr_en <= 1;
        #50 wr_en <=0;
        
         #90 din <=33;
        #120 wr_en <= 1;
       
        #50 wr_en <=0;
        #100 $stop;
    end
    always #1 clk = ~clk;
    uart_test_9600  uu(clk,rst,din,dout,wr_en);
endmodule