fulladder.vhd

这是一个4位全加器

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY FullAdder IS
PORT(dataA,dataB,carryin:IN STD_LOGIC;
	sum,carryout:OUT STD_LOGIC);
END ENTITY FullAdder;

ARCHITECTURE dataflow OF FullAdder IS
COMPONENT HalfAdder
PORT(dataA:IN STD_LOGIC;
	dataB:IN STD_LOGIC;
	sum:OUT STD_LOGIC;
	carry:OUT STD_LOGIC);
END COMPONENT; 
SIGNAL tmp_sum,tmp_carry1,tmp_carry2:STD_LOGIC;
BEGIN
u1:HalfAdder PORT MAP (dataA,dataB,tmp_sum,tmp_carry1);
u2:HalfAdder PORT MAP (tmp_sum,carryin,sum,tmp_carry2);
carryout<=(tmp_carry2 OR tmp_carry1);
END ARCHITECTURE dataflow;