halfadder.vhd

这是一个4位全加器

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY HalfAdder IS
PORT(dataA,dataB:IN STD_LOGIC;
	carry,sum:OUT STD_LOGIC);
END ENTITY HalfAdder;

ARCHITECTURE dataflow OF HalfAdder IS
BEGIN
carry<=(dataA AND dataB);
sum<=(dataA XOR dataB);
END ARCHITECTURE dataflow;