div_js.vhd

来自「技术分频器。把时钟分为奇数个」· VHDL 代码 · 共 36 行

library ieee;
use ieee.std_logic_1164.all;
entity div_js is
	generic(n : integer :=25);
	port(clk : in std_logic;
		 clkout : out std_logic);
end;

architecture rtl of div_js is
signal count1: integer range 0 to n/2;
signal count2: integer range 0 to n/2;
signal tmp1  : std_logic :='0';
signal tmp2  : std_logic :='0';
begin
	p1:process(clk)
	begin
		if(clk'event and clk='1' and clk'last_value='0') then
			if(count1=n/2-1) then
				tmp1<=not tmp1;
				count1<=0;
			else
				count1<=count1+1;
			end if;
		end if;
		
		if(clk'event and clk='0' and clk'last_value='1') then
			if(count2=n/2-1) then
				tmp2<=not tmp2;
				count2<=0;
			else
				count2<=count2+1;
			end if;
		end if;
	clkout <= tmp1 or tmp2;
	end process;	
end;