pulse_16_sum.map.qmsg

来自「采用Verilog HDL语言编写的步进电机位置系统」· QMSG 代码 · 共 5 行

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.2 Build 157 12/07/2004 SJ Full Version " "Info: Version 4.2 Build 157 12/07/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jul 20 20:46:17 2006 " "Info: Processing started: Thu Jul 20 20:46:17 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --import_settings_files=on --export_settings_files=off pulse_16_sum -c pulse_16_sum --convert_bdf_to_verilog=pulse_16_sum.bdf " "Info: Command: quartus_map --import_settings_files=on --export_settings_files=off pulse_16_sum -c pulse_16_sum --convert_bdf_to_verilog=pulse_16_sum.bdf" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "pulse_16_sum.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file pulse_16_sum.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 pulse_16_sum " "Info: Found entity 1: pulse_16_sum" {  } { { "pulse_16_sum.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_16_sum/pulse_16_sum.bdf" { } } }  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Jul 20 20:46:18 2006 " "Info: Processing ended: Thu Jul 20 20:46:18 2006" {  } {  } 0} { "I