sum_control.fit.summary

采用Verilog HDL语言编写的步进电机位置系统

Flow Status : Successful - Thu Jul 20 23:54:16 2006
Quartus II Version : 4.2 Build 157 12/07/2004 SJ Full Version
Revision Name : sum_control
Top-level Entity Name : sum_control
Family : MAX7000S
Met timing requirements : N/A
Total macrocells : 71 / 128 ( 55 % )
Total pins : 31 / 68 ( 45 % )
Device : EPM7128SLC84-6
Timing Models : Final