sum_control.tan.rpt

采用Verilog HDL语言编写的步进电机位置系统

+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EPM7128SLC84-6     ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minumum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Clock Analysis Only                                   ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off clear and preset signal paths                 ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; Off                ;      ;    ;             ;
; Do Min/Max analysis using Rise/Fall delays            ; Off                ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Use Clock Latency for PLL offset                      ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+--------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                               ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; pulse_sum_in    ;                    ; User Pin ; NONE             ; NONE     ; N/A                   ; N/A                 ; N/A    ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'pulse_sum_in'                                                                                                                                                                                                                                                                         ;
+-----------------------------------------+-----------------------------------------------------+-----------------------------------------+-----------------------------------------+--------------+--------------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                    ; To                                      ; From Clock   ; To Clock     ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+-----------------------------------------+-----------------------------------------+--------------+--------------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; 54.35 MHz ( period = 18.400 ns )                    ; lpm_counter:step_counter_rtl_0|dffs[4]  ; out_control                             ; pulse_sum_in ; pulse_sum_in ; None                        ; None                      ; 16.000 ns               ;
; N/A                                     ; 54.64 MHz ( period = 18.300 ns )                    ; lpm_counter:step_counter_rtl_0|dffs[0]  ; out_control                             ; pulse_sum_in ; pulse_sum_in ; None                        ; None                      ; 15.900 ns               ;
; N/A                                     ; 54.64 MHz ( period = 18.300 ns )                    ; lpm_counter:step_counter_rtl_0|dffs[8]  ; out_control                             ; pulse_sum_in ; pulse_sum_in ; None                        ; None                      ; 15.900 ns               ;
; N/A                                     ; 54.64 MHz ( period = 18.300 ns )                    ; lpm_counter:step_counter_rtl_0|dffs[7]  ; out_control                             ; pulse_sum_in ; pulse_sum_in ; None                        ; None                      ; 15.900 ns               ;
; N/A                                     ; 54.64 MHz ( period = 18.300 ns )                    ; lpm_counter:step_counter_rtl_0|dffs[6]  ; out_control                             ; pulse_sum_in ; pulse_sum_in ; None                        ; None                      ; 15.900 ns               ;
; N/A                                     ; 54.64 MHz ( period = 18.300 ns )                    ; lpm_counter:step_counter_rtl_0|dffs[5]  ; out_control                             ; pulse_sum_in ; pulse_sum_in ; None                        ; None                      ; 15.900 ns               ;
; N/A                                     ; 54.64 MHz ( period = 18.300 ns )                    ; lpm_counter:step_counter_rtl_0|dffs[3]  ; out_control                             ; pulse_sum_in ; pulse_sum_in ; None                        ; None                      ; 15.900 ns               ;
; N/A                                     ; 54.64 MHz ( period = 18.300 ns )                    ; lpm_counter:step_counter_rtl_0|dffs[9]  ; out_control                             ; pulse_sum_in ; pulse_sum_in ; None                        ; None                      ; 15.900 ns               ;
; N/A                                     ; 54.64 MHz ( period = 18.300 ns )                    ; lpm_counter:step_counter_rtl_0|dffs[2]  ; out_control                             ; pulse_sum_in ; pulse_sum_in ; None                        ; None                      ; 15.900 ns               ;
; N/A                                     ; 54.64 MHz ( period = 18.300 ns )                    ; lpm_counter:step_counter_rtl_0|dffs[1]  ; out_control                             ; pulse_sum_in ; pulse_sum_in ; None                        ; None                      ; 15.900 ns               ;
; N/A                                     ; 54.64 MHz ( period = 18.300 ns )                    ; lpm_counter:step_counter_rtl_0|dffs[11] ; out_control                             ; pulse_sum_in ; pulse_sum_in ; None                        ; None                      ; 15.900 ns               ;
; N/A                                     ; 54.64 MHz ( period = 18.300 ns )                    ; lpm_counter:step_counter_rtl_0|dffs[12] ; out_control                             ; pulse_sum_in ; pulse_sum_in ; None                        ; None                      ; 15.900 ns               ;
; N/A                                     ; 54.64 MHz ( period = 18.300 ns )                    ; lpm_counter:step_counter_rtl_0|dffs[15] ; out_control                             ; pulse_sum_in ; pulse_sum_in ; None                        ; None                      ; 15.900 ns               ;
; N/A                                     ; 54.64 MHz ( period = 18.300 ns )                    ; lpm_counter:step_counter_rtl_0|dffs[16] ; out_control                             ; pulse_sum_in ; pulse_sum_in ; None                        ; None                      ; 15.900 ns               ;
; N/A                                     ; 54.64 MHz ( period = 18.300 ns )                    ; lpm_counter:step_counter_rtl_0|dffs[17] ; out_control                             ; pulse_sum_in ; pulse_sum_in ; None                        ; None                      ; 15.900 ns               ;
; N/A                                     ; 54.64 MHz ( period = 18.300 ns )                    ; lpm_counter:step_counter_rtl_0|dffs[18] ; out_control                             ; pulse_sum_in ; pulse_sum_in ; None                        ; None                      ; 15.900 ns               ;
; N/A                                     ; 54.64 MHz ( period = 18.300 ns )                    ; lpm_counter:step_counter_rtl_0|dffs[19] ; out_control                             ; pulse_sum_in ; pulse_sum_in ; None                        ; None                      ; 15.900 ns               ;