main.fit.summary

采用Verilog HDL语言编写的步进电机位置系统

Flow Status : Successful - Wed Aug 02 16:41:37 2006
Quartus II Version : 4.2 Build 157 12/07/2004 SJ Full Version
Revision Name : main
Top-level Entity Name : main
Family : ACEX1K
Met timing requirements : N/A
Total logic elements : 212 / 576 ( 36 % )
Total pins : 60 / 66 ( 90 % )
Total memory bits : 0 / 12,288 ( 0 % )
Total PLLs : 0 / 1 ( 0 % )
Device : EP1K10TC100-1
Timing Models : Final