main.tan.qmsg

采用Verilog HDL语言编写的步进电机位置系统

{ "Warning" "WTAN_FOUND_COMB_LATCHES" "" "Warning: Timing Analysis found one or more latches implemented as combinational loops" { { "Warning" "WTAN_COMB_LATCH_NODE" "pulse_sum:inst4\|pulse_1\[3\] " "Warning: Node \"pulse_sum:inst4\|pulse_1\[3\]\" is a latch" {  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } }  } 0} { "Warning" "WTAN_COMB_LATCH_NODE" "pulse_sum:inst4\|pulse_1\[4\] " "Warning: Node \"pulse_sum:inst4\|pulse_1\[4\]\" is a latch" {  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } }  } 0} { "Warning" "WTAN_COMB_LATCH_NODE" "pulse_sum:inst4\|pulse_1\[5\] " "Warning: Node \"pulse_sum:inst4\|pulse_1\[5\]\" is a latch" {  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } }  } 0} { "Warning" "WTAN_COMB_LATCH_NODE" "pulse_sum:inst4\|pulse_1\[6\] " "Warning: Node \"pulse_sum:inst4\|pulse_1\[6\]\" is a latch" {  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } }  } 0} { "Warning" "WTAN_COMB_LATCH_NODE" "pulse_sum:inst4\|pulse_1\[0\] " "Warning: Node \"pulse_sum:inst4\|pulse_1\[0\]\" is a latch" {  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } }  } 0} { "Warning" "WTAN_COMB_LATCH_NODE" "pulse_sum:inst4\|pulse_1\[1\] " "Warning: Node \"pulse_sum:inst4\|pulse_1\[1\]\" is a latch" {  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } }  } 0} { "Warning" "WTAN_COMB_LATCH_NODE" "pulse_sum:inst4\|pulse_1\[2\] " "Warning: Node \"pulse_sum:inst4\|pulse_1\[2\]\" is a latch" {  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } }  } 0} { "Warning" "WTAN_COMB_LATCH_NODE" "pulse_sum:inst4\|pulse_1\[11\] " "Warning: Node \"pulse_sum:inst4\|pulse_1\[11\]\" is a latch" {  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } }  } 0} { "Warning" "WTAN_COMB_LATCH_NODE" "pulse_sum:inst4\|pulse_1\[12\] " "Warning: Node \"pulse_sum:inst4\|pulse_1\[12\]\" is a latch" {  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } }  } 0} { "Warning" "WTAN_COMB_LATCH_NODE" "pulse_sum:inst4\|pulse_1\[13\] " "Warning: Node \"pulse_sum:inst4\|pulse_1\[13\]\" is a latch" {  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } }  } 0} { "Warning" "WTAN_COMB_LATCH_NODE" "pulse_sum:inst4\|pulse_1\[14\] " "Warning: Node \"pulse_sum:inst4\|pulse_1\[14\]\" is a latch" {  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } }  } 0} { "Warning" "WTAN_COMB_LATCH_NODE" "pulse_sum:inst4\|pulse_1\[7\] " "Warning: Node \"pulse_sum:inst4\|pulse_1\[7\]\" is a latch" {  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } }  } 0} { "Warning" "WTAN_COMB_LATCH_NODE" "pulse_sum:inst4\|pulse_1\[8\] " "Warning: Node \"pulse_sum:inst4\|pulse_1\[8\]\" is a latch" {  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } }  } 0} { "Warning" "WTAN_COMB_LATCH_NODE" "pulse_sum:inst4\|pulse_1\[9\] " "Warning: Node \"pulse_sum:inst4\|pulse_1\[9\]\" is a latch" {  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } }  } 0} { "Warning" "WTAN_COMB_LATCH_NODE" "pulse_sum:inst4\|pulse_1\[10\] " "Warning: Node \"pulse_sum:inst4\|pulse_1\[10\]\" is a latch" {  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "pulse_sum:inst4\|pulse_1\[6\] " "Info: Node \"pulse_sum:inst4\|pulse_1\[6\]\"" {  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } }  } 0}  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "pulse_sum:inst4\|pulse_1\[5\] " "Info: Node \"pulse_sum:inst4\|pulse_1\[5\]\"" {  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } }  } 0}  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "pulse_sum:inst4\|pulse_1\[4\] " "Info: Node \"pulse_sum:inst4\|pulse_1\[4\]\"" {  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } }  } 0}  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "pulse_sum:inst4\|pulse_1\[3\] " "Info: Node \"pulse_sum:inst4\|pulse_1\[3\]\"" {  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } }  } 0}  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v" 22 -1 0 } }  } 0}