📄 main.map.rpt
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+----------------------------------------------------------------+
; WYSIWYG Cells ;
+--------------------------------------------------------+-------+
; Statistic ; Value ;
+--------------------------------------------------------+-------+
; Number of WYSIWYG cells ; 63 ;
; Number of synthesis-generated cells ; 149 ;
; Number of WYSIWYG LUTs ; 63 ;
; Number of synthesis-generated LUTs ; 148 ;
; Number of WYSIWYG registers ; 63 ;
; Number of synthesis-generated registers ; 16 ;
; Number of cells with combinational logic only ; 133 ;
; Number of cells with registers only ; 1 ;
; Number of cells with combinational logic and registers ; 78 ;
+--------------------------------------------------------+-------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+-------------------------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+--------------------------------------------------------------------------------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name ;
+-------------------------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+--------------------------------------------------------------------------------------------+
; |main ; 212 (2) ; 79 ; 0 ; 60 ; 133 (2) ; 1 (0) ; 78 (0) ; 117 (0) ; |main ;
; |counter_16_bits:inst1| ; 21 (5) ; 16 ; 0 ; 0 ; 5 (5) ; 0 (0) ; 16 (0) ; 16 (0) ; |main|counter_16_bits:inst1 ;
; |lpm_counter:counter_out_rtl_2| ; 16 (0) ; 16 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 16 (0) ; 16 (0) ; |main|counter_16_bits:inst1|lpm_counter:counter_out_rtl_2 ;
; |alt_counter_f10ke:wysi_counter| ; 16 (16) ; 16 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 16 (16) ; 16 (16) ; |main|counter_16_bits:inst1|lpm_counter:counter_out_rtl_2|alt_counter_f10ke:wysi_counter ;
; |fdiv:inst| ; 30 (7) ; 23 ; 0 ; 0 ; 7 (7) ; 0 (0) ; 23 (0) ; 23 (0) ; |main|fdiv:inst ;
; |lpm_counter:CNT_rtl_1| ; 23 (0) ; 23 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 23 (0) ; 23 (0) ; |main|fdiv:inst|lpm_counter:CNT_rtl_1 ;
; |alt_counter_f10ke:wysi_counter| ; 23 (23) ; 23 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 23 (23) ; 23 (23) ; |main|fdiv:inst|lpm_counter:CNT_rtl_1|alt_counter_f10ke:wysi_counter ;
; |pulse_sum:inst4| ; 42 (42) ; 0 ; 0 ; 0 ; 42 (42) ; 0 (0) ; 0 (0) ; 0 (0) ; |main|pulse_sum:inst4 ;
; |second_pulse_latch:inst3| ; 45 (15) ; 15 ; 0 ; 0 ; 30 (0) ; 0 (0) ; 15 (15) ; 30 (0) ; |main|second_pulse_latch:inst3 ;
; |lpm_add_sub:add_rtl_4| ; 15 (0) ; 0 ; 0 ; 0 ; 15 (0) ; 0 (0) ; 0 (0) ; 15 (0) ; |main|second_pulse_latch:inst3|lpm_add_sub:add_rtl_4 ;
; |addcore:adder| ; 15 (1) ; 0 ; 0 ; 0 ; 15 (1) ; 0 (0) ; 0 (0) ; 15 (1) ; |main|second_pulse_latch:inst3|lpm_add_sub:add_rtl_4|addcore:adder ;
; |a_csnbuffer:result_node| ; 14 (14) ; 0 ; 0 ; 0 ; 14 (14) ; 0 (0) ; 0 (0) ; 14 (14) ; |main|second_pulse_latch:inst3|lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node ;
; |lpm_add_sub:add_rtl_5| ; 15 (0) ; 0 ; 0 ; 0 ; 15 (0) ; 0 (0) ; 0 (0) ; 15 (0) ; |main|second_pulse_latch:inst3|lpm_add_sub:add_rtl_5 ;
; |addcore:adder| ; 15 (1) ; 0 ; 0 ; 0 ; 15 (1) ; 0 (0) ; 0 (0) ; 15 (1) ; |main|second_pulse_latch:inst3|lpm_add_sub:add_rtl_5|addcore:adder ;
; |a_csnbuffer:result_node| ; 14 (14) ; 0 ; 0 ; 0 ; 14 (14) ; 0 (0) ; 0 (0) ; 14 (14) ; |main|second_pulse_latch:inst3|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node ;
; |sum_control:inst5| ; 72 (24) ; 25 ; 0 ; 0 ; 47 (23) ; 1 (1) ; 24 (0) ; 48 (0) ; |main|sum_control:inst5 ;
; |lpm_add_sub:add_rtl_3| ; 24 (0) ; 0 ; 0 ; 0 ; 24 (0) ; 0 (0) ; 0 (0) ; 24 (0) ; |main|sum_control:inst5|lpm_add_sub:add_rtl_3 ;
; |addcore:adder| ; 24 (1) ; 0 ; 0 ; 0 ; 24 (1) ; 0 (0) ; 0 (0) ; 24 (1) ; |main|sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder ;
; |a_csnbuffer:result_node| ; 23 (23) ; 0 ; 0 ; 0 ; 23 (23) ; 0 (0) ; 0 (0) ; 23 (23) ; |main|sum_control:inst5|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node ;
; |lpm_counter:step_counter_rtl_0| ; 24 (0) ; 24 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 24 (0) ; 24 (0) ; |main|sum_control:inst5|lpm_counter:step_counter_rtl_0 ;
; |alt_counter_f10ke:wysi_counter| ; 24 (24) ; 24 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 24 (24) ; 24 (24) ; |main|sum_control:inst5|lpm_counter:step_counter_rtl_0|alt_counter_f10ke:wysi_counter ;
+-------------------------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+--------------------------------------------------------------------------------------------+
+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in E:/戴仙金/资料/Verilog书/源代码/step_motor/main/main.map.eqn.
+---------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+----------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Name with Absolute Path ;
+----------------------------------+-----------------+----------------------------------------------------------------------+
; main.bdf ; yes ; E:/戴仙金/资料/Verilog书/源代码/step_motor/main/main.bdf ;
; sum_control.v ; yes ; E:/戴仙金/资料/Verilog书/源代码/step_motor/main/sum_control.v ;
; pulse_sum.v ; yes ; E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_sum.v ;
; fdiv.v ; yes ; E:/戴仙金/资料/Verilog书/源代码/step_motor/main/fdiv.v ;
; pulse_16.v ; yes ; E:/戴仙金/资料/Verilog书/源代码/step_motor/main/pulse_16.v ;
; counter_16_bits.v ; yes ; E:/戴仙金/资料/Verilog书/源代码/step_motor/main/counter_16_bits.v ;
; second_pulse_latch.v ; yes ; E:/戴仙金/资料/Verilog书/源代码/step_motor/main/second_pulse_latch.v ;
; lpm_counter.tdf ; yes ; d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf ;
; lpm_constant.inc ; yes ; d:/altera/quartus42/libraries/megafunctions/lpm_constant.inc ;
; lpm_decode.inc ; yes ; d:/altera/quartus42/libraries/megafunctions/lpm_decode.inc ;
; lpm_add_sub.inc ; yes ; d:/altera/quartus42/libraries/megafunctions/lpm_add_sub.inc ;
; cmpconst.inc ; yes ; d:/altera/quartus42/libraries/megafunctions/cmpconst.inc ;
; lpm_compare.inc ; yes ; d:/altera/quartus42/libraries/megafunctions/lpm_compare.inc ;
; lpm_counter.inc ; yes ; d:/altera/quartus42/libraries/megafunctions/lpm_counter.inc ;
; dffeea.inc ; yes ; d:/altera/quartus42/libraries/megafunctions/dffeea.inc ;
; alt_synch_counter.inc ; yes ; d:/altera/quartus42/libraries/megafunctions/alt_synch_counter.inc ;
; alt_synch_counter_f.inc ; yes ; d:/altera/quartus42/libraries/megafunctions/alt_synch_counter_f.inc ;
; alt_counter_f10ke.inc ; yes ; d:/altera/quartus42/libraries/megafunctions/alt_counter_f10ke.inc ;
; alt_counter_stratix.inc ; yes ; d:/altera/quartus42/libraries/megafunctions/alt_counter_stratix.inc ;
; aglobal42.inc ; yes ; d:/altera/quartus42/libraries/megafunctions/aglobal42.inc ;
; alt_counter_f10ke.tdf ; yes ; d:/altera/quartus42/libraries/megafunctions/alt_counter_f10ke.tdf ;
; flex10ke_lcell.inc ; yes ; d:/altera/quartus42/libraries/megafunctions/flex10ke_lcell.inc ;
; lpm_add_sub.tdf ; yes ; d:/altera/quartus42/libraries/megafunctions/lpm_add_sub.tdf ;
; addcore.inc ; yes ; d:/altera/quartus42/libraries/megafunctions/addcore.inc ;
; look_add.inc ; yes ; d:/altera/quartus42/libraries/megafunctions/look_add.inc ;
; bypassff.inc ; yes ; d:/altera/quartus42/libraries/megafunctions/bypassff.inc ;
; altshift.inc ; yes ; d:/altera/quartus42/libraries/megafunctions/altshift.inc ;
; alt_stratix_add_sub.inc ; yes ; d:/altera/quartus42/libraries/megafunctions/alt_stratix_add_sub.inc ;
; alt_mercury_add_sub.inc ; yes ; d:/altera/quartus42/libraries/megafunctions/alt_mercury_add_sub.inc ;
; addcore.tdf ; yes ; d:/altera/quartus42/libraries/megafunctions/addcore.tdf ;
; a_csnbuffer.inc ; yes ; d:/altera/quartus42/libraries/megafunctions/a_csnbuffer.inc ;
; a_csnbuffer.tdf ; yes ; d:/altera/quartus42/libraries/megafunctions/a_csnbuffer.tdf ;
; altshift.tdf ; yes ; d:/altera/quartus42/libraries/megafunctions/altshift.tdf ;
+----------------------------------+-----------------+----------------------------------------------------------------------+
+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+-----------------------------------+---------+
; Resource ; Usage ;
+-----------------------------------+---------+
; Logic cells ; 212 ;
; Total combinational functions ; 211 ;
; Total 4-input functions ; 63 ;
; Total 3-input functions ; 30 ;
; Total 2-input functions ; 54 ;
; Total 1-input functions ; 64 ;
; Total 0-input functions ; 0 ;
; Combinational cells for routing ; 0 ;
; Total registers ; 79 ;
; Total logic cells in carry chains ; 117 ;
; I/O pins ; 60 ;
; Maximum fan-out node ; Reset ;
; Maximum fan-out ; 36 ;
; Total fan-out ; 716 ;
; Average fan-out ; 2.63 ;
+-----------------------------------+---------+
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 4.2 Build 157 12/07/2004 SJ Full Version
Info: Processing started: Wed Aug 02 16:41:08 2006
Info: Command: quartus_map --import_settings_files=on --export_settings_files=off main -c main
Info: Found 0 design units, including 0 entities, in source file main.v
Info: Found 1 design units, including 1 entities, in source file main.bdf
Info: Found entity 1: main
Info: Using design file sum_control.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
Info: Found entity 1: sum_control
Info: Using design file pulse_sum.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
Info: Found entity 1: pulse_sum
Warning: Verilog HDL Always Construct warning at pulse_sum.v(20): variable cnt may not be assigned a new value in every possible path through the Always Construct. Variable cnt holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: Verilog HDL Always Construct warning at pulse_sum.v(20): variable pulse_1 may not be assigned a new value in every possible path through the Always Construct. Variable pulse_1 holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: Tied undriven net "pulse_1[15]" at pulse_sum.v(17) to GND or VCC
Info: Using design file fdiv.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
Info: Found entity 1: fdiv
Info: Using design file pulse_16.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
Info: Found entity 1: pulse_16
Info: Using design file counter_16_bits.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
Info: Found entity 1: counter_16_bits
Info: Using design file second_pulse_latch.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
Info: Found entity 1: second_pulse_latch
Warning: Verilog HDL unsupported feature warning at second_pulse_latch.v(21): Initial Construct is not supported and will be ignored
Info: Inferred 3 megafunctions from design logic
Info: Inferred lpm_counter megafunction (LPM_WIDTH=24) from the following logic: "sum_control:inst5|step_counter[0]~72"
Info: Inferred lpm_counter megafunction (LPM_WIDTH=23) from the following logic: "fdiv:inst|CNT[0]~69"
Info: Inferred lpm_counter megafunction (LPM_WIDTH=16) from the following logic: "counter_16_bits:inst1|counter_out[0]~16"
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf
Info: Found entity 1: lpm_counter
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus42/libraries/megafunctions/alt_counter_f10ke.tdf
Info: Found entity 1: alt_counter_f10ke
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus42/libraries/megafunctions/lpm_add_sub.tdf
Info: Found entity 1: lpm_add_sub
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus42/libraries/megafunctions/addcore.tdf
Info: Found entity 1: addcore
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus42/libraries/megafunctions/a_csnbuffer.tdf
Info: Found entity 1: a_csnbuffer
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus42/libraries/megafunctions/altshift.tdf
Info: Found entity 1: altshift
Warning: Design contains 17 input pin(s) that do not drive logic
Warning: No output dependent on input pin "Initial_Speed[15]"
Warning: No output dependent on input pin "Initial_Speed[14]"
Warning: No output dependent on input pin "Initial_Speed[13]"
Warning: No output dependent on input pin "Initial_Speed[12]"
Warning: No output dependent on input pin "Initial_Speed[11]"
Warning: No output dependent on input pin "Initial_Speed[10]"
Warning: No output dependent on input pin "Initial_Speed[9]"
Warning: No output dependent on input pin "Initial_Speed[8]"
Warning: No output dependent on input pin "Initial_Speed[7]"
Warning: No output dependent on input pin "Initial_Speed[6]"
Warning: No output dependent on input pin "Initial_Speed[5]"
Warning: No output dependent on input pin "Initial_Speed[4]"
Warning: No output dependent on input pin "Initial_Speed[3]"
Warning: No output dependent on input pin "Initial_Speed[2]"
Warning: No output dependent on input pin "Initial_Speed[1]"
Warning: No output dependent on input pin "Initial_Speed[0]"
Warning: No output dependent on input pin "Acceleration[15]"
Info: Implemented 272 device resources after synthesis - the final resource count might be different
Info: Implemented 59 input pins
Info: Implemented 1 output pins
Info: Implemented 212 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 22 warnings
Info: Processing ended: Wed Aug 02 16:41:20 2006
Info: Elapsed time: 00:00:13
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